Typical active current: 2 mA (Automotive-A) at f = 1 MHz
[1]
and OE features
■
Easy memory expansion with CE
■
■
■
current. It is ideal for providing More Battery Life™ (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device in standby mode reduces power consumption
by more than 99 percent when deselected (CE HIGH or both BLE
and BHE are HIGH). The input and output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when:
■
■
■
■
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 48-ball very fine ball grid array (VFBGA)
(single/dual CE option) and 44-pin thin small outline package
(TSOP) II packages
Byte power-down feature
■
Functional Description
The CY62147EV30 is a high-performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O
0
to I/O
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See the
Truth Table on page 12
for a
complete description of read and write modes.
For a complete list of related resources,
click here.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
POWER DOWN
CIRCUIT
CE
A
12
A
11
A
13
A
15
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
1
and
CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
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