CY22801
Universal Programmable Clock Generator
(UPCG)
Universal Programmable Clock Generator (UPCG)
Features
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Functional Description
The CY22801 is a flash-programmable clock generator that
supports various applications in consumer and communications
markets. The device uses the Cypress-proprietary PLL along
with Spread Spectrum and VCXO technology to make it one of
the most versatile clock synthesizers in the market. The device
uses a Cypress-proprietary PLL to drive up to three configurable
outputs in an 8-pin SOIC.
The CY22801 is programmed with an easy-to-use programmer
dongle, the CY36800, in conjunction with the CyClocksRT™
software. This enables fast sample generation of prototype
builds for user-defined frequencies. Cypress’s value-added
distribution partners and third-party programming systems from
BP Microsystems, HiLo Systems, and others, can also be
contacted for large production quantities. A JEDEC file needs to
be configured to program CY22801, which can be generated
using the CyClocksRT™ software.
For a complete list of related documentation, click
here.
Integrated phase-locked loop (PLL)
Field-Programmable
Input frequency range:
❐
Crystal: 8 MHz to 30 MHz
❐
CLKIN: 1 MHz to 133 MHz
Low-voltage complementary metal oxide semiconductor
(LVCMOS) output frequency:
❐
Up to 200 MHz (commercial grade)
❐
Up to 166.6 MHz (industrial grade)
Special Features:
❐
Spread Spectrum
❐
VCXO
❐
Inputs: PD or OE, FS
Low-jitter, high-accuracy outputs
3.3 V operation
Commercial and industrial temperature ranges
8-pin small-outline integrated circuit (SOIC) package
Serial interface for device configuration
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Logic Block Diagram
XIN/CLKIN
XOUT
SDAT/FS0/
VCXO/OE
/PD#
VCXO
VCXO
REF
with Logic
Serial I/F
with
Control
Logic
PLL
Divider
1
Switch
Matrix
Divider
2
CLKA
FS2
SCLK
/FS1
SDAT
/FS0
/PD#
CLKB/
FS1/
SCLK
CLKC
/FS2
OE
Cypress Semiconductor Corporation
Document Number: 001-15571 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 26, 2015
CY22801
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
External Reference Crystal/Clock Input ......................... 4
Output Clock Frequencies ............................................... 4
VCXO ................................................................................. 4
VCXO Profile ............................................................... 4
Spread Spectrum Clock Generation (SSCG) ................. 4
Spread Percentage ..................................................... 4
Modulation Frequency ................................................. 4
SSON Pin .................................................................... 4
Multifunction Pins ............................................................ 5
Frequency Calculation and Register Definitions ........... 5
Default Startup Condition for the CY22801 .................... 6
Frequency Calculations and Register Definitions
using the Serial (I2C) Interface ........................................ 6
Reference Frequency .................................................. 6
Programmable Crystal Input Oscillator Gain Settings . 6
Using an External Clock as the Reference Input ......... 7
Input Load Capacitors ................................................. 8
PLL Frequency, Q Counter [42H(6..0)] ....................... 8
PLL Frequency, P Counter
[40H(1..0)], [41H(7..0)], [42H(7)] ......................................... 9
PLL Post Divider Options [0CH(7..0)], [47H(7..0)] ....... 9
Charge Pump Settings [40H(2..0)] .............................. 9
Clock Output Settings:
CLKSRC – Clock Output Crosspoint Switch Matrix
[44H(7..0)], [45H(7..0)], [46H(7..6)] ................................... 10
Test, Reserved, and Blank Registers ........................ 10
Application Guideline ..................................................... 12
Best Practices for Best Jitter Performance ................ 12
Field Programming the CY22801 .................................. 12
CyClocksRT Software .................................................... 12
Possible Configuration Examples ................................ 12
Informational Graphs ..................................................... 13
Absolute Maximum Conditions ..................................... 14
Recommended Operating Conditions .......................... 14
Recommended Crystal Specifications
for non-VCXO Applications ........................................... 14
Pullable Crystal Specifications
for VCXO Application only ............................................. 14
DC Electrical Specifications .......................................... 15
AC Electrical Characteristics ........................................ 16
Test Circuit ...................................................................... 17
Timing Definitions .......................................................... 17
2-wire Serial (I2C) Interface Timing ............................... 18
Data Valid .................................................................. 18
Data Frame ............................................................... 18
Acknowledge Pulse ................................................... 18
Ordering Information ...................................................... 20
Possible Configurations ............................................. 20
Ordering Code Definitions ......................................... 20
Package Diagram ............................................................ 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 001-15571 Rev. *L
Page 2 of 25
CY22801
Pin Configurations
Figure 1. CY22801 8-pin SOIC pinout
XIN/CLKIN
V
DD
SDAT/FS0/
VCXO/OE/PD#
V
SS
1
2
3
4
CY22801
8
7
6
5
XOUT
CLKC/FS2
CLKA
CLKB/FS1/SCLK
Pin Definitions
Name
CLKIN /
XIN
V
DD
SDAT / FS0
/ VCXO /
OE / PD#
V
SS
CLKB / FS1
/ SCLK
CLKA
CLKC /
FS2
XOUT
Pin Number
1
2
3
Description
External reference crystal input / external reference clock input
3.3 V voltage supply
Serial interface data line / frequency select 0 / VCXO analog control voltage / Output Enable /
Power-down
Ground
Clock output B / frequency select 1 / serial interface clock line
Clock output A
Clock output C / frequency select 3 / V
SS
External reference crystal output: Connect to external crystal. When the reference is an external clock
signal (applied to pin 1), this pin is not used and must be left floating.
4
5
6
7
8
Document Number: 001-15571 Rev. *L
Page 3 of 25
CY22801
External Reference Crystal/Clock Input
CY22801 can accept external reference clock input as well as
crystal input. External reference clock input frequency range is
from 1 MHz to 133 MHz.
The input crystal oscillator of the CY22801 is an important
feature because of the flexibility it provides in selecting a crystal
as a reference clock source. The oscillator inverter has
programmable gain, enabling maximum compatibility with a
reference crystal, based on manufacturer, process,
performance, and quality.
Input load capacitors are placed on the CY22801 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when non-linear load capacitance is affected by load,
bias, supply, and temperature changes.
The value of the input load capacitors is determined by eight bits
in a programmable register. Total load capacitance is determined
by the formula:
CapLoad = (C
L
– C
BRD
– C
CHIP
) / 0.09375 pF
In CyClocksRT, enter the crystal capacitance (C
L
). The value of
CapLoad is determined automatically and programmed into the
CY22801.
VCXO is not compatible with Spread spectrum and Serial
Interface.
VCXO Profile
Figure 3
shows an example of a VCXO profile. The analog
voltage input is on the X-axis and the PPM range is on the Y-axis.
An increase in the VCXO input voltage results in a corresponding
increase in the output frequency. This moves the PPM from a
negative to positive offset.
Figure 3. VCXO Profile
200
150
100
Tuning [ppm]
50
0
-50
-100
-150
-200
VCXO input [V]
0
0.5
1
1.5
2
2.5
3
3.5
Output Clock Frequencies
The CY22801 is a very flexible clock generator with up to three
individual outputs, generated from an integrated PLL. See
Figure 2
for details.
The output of the PLL runs at high frequency and is divided down
to generate the output clocks. Two programmable dividers are
available for this purpose. Therefore, although the output clocks
may have different frequencies, they must be related, based on
the PLL frequency.
It is also possible to direct the reference clock input to any of the
outputs, thereby bypassing the PLL. Lastly, the reference clock
may be passed through either divider.
Figure 2. Basic PLL Block Diagram
Post
Divider
1N
Crosspoint
Switch
Matrix
Spread Spectrum Clock Generation (SSCG)
Spread spectrum clock generation (SSCG) in CY22801 helps to
reduce EMI found in today’s high-speed digital electronic
systems.
The device uses the proprietary spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the
input clock. By modulating the frequency of the clock, the
measured EMI at the fundamental and harmonic frequencies is
greatly reduced. This reduction in radiated energy can
significantly reduce the cost of complying with the regulatory
agency electromagnetic compatibility (EMC) requirements and
improve time to market without degrading system performance.
Programmed spread spectrum modulation will appear same on
all three clock outputs as they come from same PLL even if
operating at different frequencies. Spread spectrum is not
compatible with VCXO feature.
REF
(XIN/CLKIN)
/Q
PFD
VCO
CLKA
CLKB
CLKC
/P
Post
Divider
2N
Spread Percentage
The percentage of spread can be programmed from ±0.25% to
±2.5% for center spread and from –0.5% to –5.0% for down
spread. The granularity is 0.25%.
Modulation Frequency
VCXO
One of the key components of the CY22801 device is the VCXO.
The VCXO is used to ‘pull’ the reference crystal higher or lower
to lock the system frequency to an external source. This is ideal
for applications where the output frequency needs to track along
with an external reference frequency that is constantly shifting.
A special pullable crystal must be used to have adequate VCXO
pull range. Pullable crystal specifications are included in this
data sheet.
Document Number: 001-15571 Rev. *L
The default modulation frequency is 31.5 kHz. Other modulation
frequencies available through configuration software are
30.1 kHz and 32.9 kHz.
SSON Pin
SSON pin functionality can be used to turn Spread ON and OFF
in clock output. Any one of the Multifunction pins can be
configured as SSON pin.
Page 4 of 25
CY22801
Multifunction Pins
There are three pins
with multiple functions either as control
pins or as output pins. The following are the acronyms used for
the different control function pins:
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[1]
Table 2. Possible Combinations for Multifunction Pins
Possible Combinations
A
B
C
D
E
F
G
H
Pin#3
FS0
FS0
FS0
OE / PD#
OE / PD#
OE / PD#
SDAT
VCXO
Pin#5
CLKB
CLKB
FS1
CLKB
FS1
FS1
SCLK
CLKB
Pin#7
CLKC
FS2
FS2
CLKC
CLKC
FS2
CLKC
CLKC
Output enable (OE): If OE = 1, all outputs are enabled
Frequency select (FS0, 1, 2): These pins can be used to select
one of the programmed clock frequencies for clock output. All
of three multifunction pins support this functionality. Any of
these pins can also be configured as Spread spectrum ON
(SSON) pin. If SSON = 1, clock output has programmed
spread; if SSON = 0, clock output does not have spread.
Power-down: active low (PD#): If PD# = 0, all outputs are
tristated and the device enters in the low-power state
Voltage controlled crystal oscillator (VCXO): Analog voltage on
this pin controls the output frequency of oscillator
Serial interface clock line (SCLK) and serial interface data line
(SDAT): These pins are for serial interface and are compatible
with I
2
C.
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Frequency Calculation and Register
Definitions
The CY22801 is an extremely flexible clock generator with four
basic variables that are used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider, which
can be a fixed or calculated value. There are three formulas to
determine the final output frequency of a CY22801 based
design:
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Each of these three multi-function pins supports selected
functions mentioned in
Table 1.
One of the supported functions
can be programmed on the pin at a time.
Table 1. Multi Function Pin Options
Pin#
3
Pin Name
SDAT / FS0 /
VCXO / OE /
PD#
CLKB / FS1 /
SCLK
CLKC / FS2
OE
Y
CLK
PD# VCXO FS OUTPUT
Y
Y
[2]
Y
[3]
N
[4]
I
2
C
SDAT
[2]
CLK = ((REF × P) / Q) / Post divider
CLK = REF / Post divider
CLK = REF
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5
7
N
N
N
N
N
N
Y
Y
Y
Y
[5]
SCLK
N
The basic PLL block diagram is shown in
Figure 4.
Each of the
three clock outputs on the CY22801 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be applied
to the calculated VCO frequency ((REF × P) / Q) or to the REF
directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Notes
1. There are Weak Pull up resistors (approximately 100 k) on all Multifunctional pins.
2. VCXO and SSON functions as well as VCXO and Serial Interface functions are not compatible.
3. ‘Y’ means pin supports this function.
4. ‘N’ means pin does not support this function.
5. Do not use this pin as Reference Clock Output.
Document Number: 001-15571 Rev. *L
Page 5 of 25
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