LNBH23L
LNB supply and control IC with step-up and I²C interface
Features
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Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @ 0.5
A)
Selectable output current limit by external
resistor
Compliant with main satellite receivers output
voltage specification
Auxiliary modulation input (EXTM pin)
facilitates DiSEqC™ 1.X encoding
Accurate built-in 22 kHz tone generator suits
widely accepted standards
Low-drop post regulator and high efficiency
step-up PWM with integrated power NMOS
allow low power losses
Overload and over-temperature internal
protections with I²C diagnostic bits
LNB short circuit dynamic protection
±
4 kV ESD tolerant on output power pins
QFN32 (5 x 5 mm)
(Exposed pad)
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■
Description
Intended for analog and digital satellite receivers,
the LNBH23L is a monolithic voltage regulator
and interface IC, assembled in QFN32 5 x 5
specifically designed to provide the 13 / 18 V
power supply and the 22 kHz tone signalling to
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
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Applications
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STB satellite receivers
TV satellite receivers
PC card satellite receivers
Table 1.
Device summary
Order code
LNBH23LQTR
Package
QFN32 (5 x 5 mm) Exposed pad
Packaging
Tape and reel
November 2010
Doc ID 15335 Rev 4
1/25
www.st.com
25
Contents
LNBH23L
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5
DiSEqC™ 1.X implementation with VOTX and EXTM pin connection . . . . 5
PDC optional circuit for DiSEQC™ 1.X applications using VOTX
signal on to EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 6
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
6.3
6.4
6.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
LNBH23L software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
7.2
7.3
7.4
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
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Doc ID 15335 Rev 4
LNBH23L
Contents
7.5
7.6
7.7
Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 15335 Rev 4
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Block diagram
LNBH23L
1
Figure 1.
Block diagram
Block diagram
ISEL
TTX
ADDR SDA SCL
V
CC
Byp V
CC-L
LX
Controller
PWM
Preregulator
+U.V.lockout
+
+P.ON reset
EN
VSEL
VSEL
TTX
EN
Rsense
P-GND
Vup
VOUT Control
I²C interface
TEN
VoRX
Linear Post-reg
+Protections
+Diagnostics
FB
VoTX
TTX
I²C OLF and OTF
Diagnostics
22kHz
Oscill.
EXTM
Pull Down
Controller
PDC
DSQIN
LNBH23L
A-GND
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Doc ID 15335 Rev 4
LNBH23L
Application information
2
Application information
This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V,
generates the voltages (V
UP
) that let the linear post-regulator to work at a minimum
dissipated power of 0.55 W typ. @ 500 mA load (the linear post-regulator drop voltage is
internally kept at V
UP
- V
OUT
= 1.1 V typ.). An under voltage lockout circuit will disable the
whole circuit when the supplied V
CC
drops below a fixed threshold (6.7 V typically).
Note:
In this document the V
OUT
is intended as the voltage present at the linear post-regulator
output (V
oRX
pin).
2.1
DiSEqC™ data encoding
The internal 22 kHz tone generator is factory trimmed in accordance to the standards, and
can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin
(DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the
22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The
TTX function must be disabled setting TTX to LOW. Besides the internal 22 kHz tone
generator, the auxiliary modulation pin (EXTM) can be driven by an external 22 kHz source
and in this case TTX must be set to low.
2.2
DiSEqC™ 1.X implementation by EXTM pin
In order to improve design flexibility and reduce the total application cost, an analogic
modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the
V
oRX
DC output voltage. An appropriate DC blocking capacitor must be used to couple the
modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter
can be removed (see
Figure 5)
saving the external components cost. If this configuration is
used keep TTX set to low.
The pin EXTM modulates the V
oRX
voltage through the series decoupling capacitor, so that:
V
oRX(AC)
= V
EXTM(AC)
x G
EXTM
Where V
oRX(AC)
and V
EXTM(AC)
are, respectively, the peak to peak voltage on the V
oRX
and
EXTM pins while G
EXTM
is the voltage gain from EXTM to V
oRX
.
2.3
DiSEqC™ 1.X implementation with V
OTX
and EXTM pin
connection
If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz
tone generator signal available through the V
oTX
pin to drive the EXTM pin. The V
oTX
pin
internal circuit must be preventively set ON by setting the TTX function to High. This can be
controlled both through the TTX pin or by I²C bit. By this way the V
oTX
22 kHz signal will be
superimposed to the V
oRX
DC voltage to generate the LNB output 22 kHz tone (see
Figure 3).
After TTX is set to High the internal 22 kHz tone generator available through the
V
oTX
pin can be activated during the 22 kHz transmission either by DSQIN pin or by the TEN
bit.The DSQIN internal circuit activates the 22 kHz tone on the V
oTX
output with 0.5 cycles ±
25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycles ± 25
µs delay after the TTL signal is expired. As soon as the tone transmission is expired, the
Doc ID 15335 Rev 4
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