Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535-01
DATA SHEET
General Description
The ICS8535-01 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The ICS8535- 01
has two single ended clock inputs. the single ended clock input
accepts LVCMOS or LVTTL input levels and translate them to 3.3V
LVPECL levels. The clock enable is internally synchronized to
eliminate runt clock pulses on the output during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8535-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• Four differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
• CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.9ns (maximum)
Pin Assignment
V
EE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
• Additive phase jitter, RMS: < 0.09ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
ICS8535-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.92 body package
G Package
Top View
V
CC
nQ0
nQ1
Q0
Q1
CLK_SEL
Q2
nQ2
Q3
nQ3
20 19 18 17 16
V
CC
nQ3
Q3
V
EE
CLK_EN
1
2
3
4
5
6
CLK_SEL
7
CLK0
8
nc
9 10
CLK1
nc
15 V
CC
14 Q2
13 nQ2
12 V
CC
11 nc
ICS8535-01
20-Lead VFQFN
4mm x 4mm x 0.9 body package
K Package
Top View
ICS8535-01 REVISION F 08/11/14
1
©2014 Integrated Device Technology, Inc.
ICS8535-01 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
Name
V
EE
CLK_EN
Power
Input
Pullup
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW,
Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input.
LVCMOS / LVTTL interface levels.
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
No connect
Positive supply pins
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
CLK_SEL
CLK0
CLK1
nc
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Unused
Power
Output
Output
Output
Output
Pulldown
Pulldown
Pulldown
NOTE 1:
Pullup
and
Pulldown
refers to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL
FANOUT BUFFER
2
REVISION F 08/11/14
ICS8535-01 DATA SHEET
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
REVISION F 08/11/14
3
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL
FANOUT BUFFER
ICS8535-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
20-Lead TSSOP
20-Lead VFQFN
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfps)
60.4°C/W (0mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High
Voltage
CLK0, CLK1
CLK_EN,
CLK_SEL
CLK0, CLK1
CLK_EN,
CLK_SEL
CLK0, CLK1,
CLK_SEL
CLK_EN
CLK0, CLK1,
CLK_SEL
CLK_EN
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
1.3
0.8
150
5
Units
V
v
V
V
µA
µA
µA
µA
V
IL
Input Low
Voltage
I
IH
Input High
Current
I
IL
Input Low
Current
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V±5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
1
Output Low Voltage
1
Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50to V
CC
– 2.
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL
FANOUT BUFFER
4
REVISION F 08/11/14
ICS8535-01 DATA SHEET
AC Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V±5%, T
A
= 0°C to 70°C
1
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay
2
Output Skew
3, 4
Part-to-Part Skew
4, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
6
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
300
48
50
0.09
700
52
ƒ
266MHz
1.0
11
Test Conditions
Minimum
Typical
Maximum
266
1.9
30
250
Units
MHz
ns
ps
ps
ps
ps
%
NOTE 1: All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output.
The part does not add jitter.
NOTE 2: Measured from the V CC /2 of the input to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: Driving only one input clock.
REVISION F 08/11/14
5
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL
FANOUT BUFFER
实时操作系统RTOS
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