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CY62146EV30LL-45ZSXAT

产品描述SRAM 4Mb 3V 45ns 256K x 16 LP SRAM
产品类别存储   
文件大小2MB,共18页
制造商Cypress(赛普拉斯)
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CY62146EV30LL-45ZSXAT概述

SRAM 4Mb 3V 45ns 256K x 16 LP SRAM

CY62146EV30LL-45ZSXAT规格参数

参数名称属性值
产品种类
Product Category
SRAM
制造商
Manufacturer
Cypress(赛普拉斯)
RoHSDetails
Memory Size4 Mbit
Organization256 k x 16
Access Time45 ns
接口类型
Interface Type
Parallel
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2.2 V
Supply Current - Max20 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TSOP-44
系列
Packaging
Cut Tape
系列
Packaging
Reel
Memory TypeSDR
Moisture SensitiveYes
工厂包装数量
Factory Pack Quantity
1000
类型
Type
Asynchronous

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CY62146EV30 MoBL
®
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
Very high speed: 45 ns
Temperature ranges
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62146DV30
Ultra low standby power
Typical standby current: 1
μA
Maximum standby current: 7
μA
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in a Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin TSOP II Packages
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL
®
) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O
0
through I/O
15
) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O
0
to I/O
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See the
Truth Table on page 11
for a
complete description of read and write modes.
For a complete list of related documentation,
click here.
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
11
A
12
A
13
A
15
A
14
A
16
A
17
Cypress Semiconductor Corporation
Document Number: 38-05567 Rev. *L
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 21, 2016

CY62146EV30LL-45ZSXAT相似产品对比

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描述 SRAM 4Mb 3V 45ns 256K x 16 LP SRAM SRAM 4Mb 3V 45ns 256K x 16 LP SRAM

 
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