FemtoClock
®
NG Universal Frequency
Translator
849N202
Datasheet
General Description
The 849N202 is a highly flexible FemtoClock® NG general purpose,
low phase noise Universal Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 0.98MHz - 312.5MHz range and most output
frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for
details). A wide range of input reference clocks and a range of
low-cost fundamental mode crystal frequencies may be used as the
source for the output frequency.
The 849N202 has three operating modes to support a very broad
spectrum of applications:
1) Frequency Synthesizer
Features
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4
TH
generation FemtoClock® NG technology
Universal Frequency Translator (UFT) / Frequency Synthesizer
Two outputs, individually programmable as LVPECL or LVDS
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Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 0.98MHz up to 1,300MHz
Zero ppm frequency translation
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
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Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
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Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 125MHz, using a 40MHz crystal
(12kHz - 20MHz): 510fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz, using a 40MHz crystal
(12kHz - 40MHz): 321fs (typical), Synthesizer Mode (Integer FB)
Output supply voltage modes:
V
CC
/V
CCA
/V
CCO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
3) Low-Bandwidth Frequency Translator
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This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
XTALBAD
CLK1BAD
V
CCA
XTAL_IN
XTAL_OUT
V
CC
CLK_SEL
CLK0
nCLK0
V
CC
V
EE
CLK1
nCLK1
1
2
3
4
5
6
7
8
9
10
40 39 38 37 36 35 34 33 32 31
30
29
nc
CLK_ACTIVE
HOLDOVER
Pin Assignment
CLK0BAD
LF1
LF0
V
EE
LOCK_IND
V
CC
OE0
Q0
nQ0
V
CCO
Q1
nQ1
OE1
V
EE
849N202
40 Lead VFQFN
6mm x 6mm x 0.925mm
K Package
Top View
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
CONFIG
S_A1
S_A0
nc
PLL_BYPASS
SDATA
V
CC
nc
SCLK
nc
©2016 Integrated Device Technology, Inc..
1
Revision B, May 20, 2016
849N202 Datasheet
Complete Block Diagram
©2016 Integrated Device Technology, Inc.
2
Revision B, May 20, 2016
849N202 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3, 7, 13, 29
Name
XTAL_IN
XTAL_OUT
V
CC
CLK_SEL
Input
Power
Type
Description
Crystal Oscillator interface designed for 12pF parallel resonant crystals.
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input. LVCMOS/LVTTL
interface levels.
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Negative supply pins.
Pulldown
Pullup/
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
No connect. These pins are to be left unconnected.
Bypasses the VCXO PLL. In bypass mode, outputs are clocked off the falling
edge of the input reference. LVCMOS/LVTTL interface levels.
0 = PLL Mode (default)
1 = PLL Bypassed
I
2
C Data Input/Output. Open drain.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Configuration Pin. Selects between one of two factory programmable pre-set
power-up default configurations. The two configurations can have different
output/input frequency translation ratios, different PLL loop bandwidths, etc.
These default configurations can be overwritten after power-up via I
2
C if the user
so desires. LVCMOS/LVTTL interface levels.
0 = Configuration 0 (default)
1 = Configuration 1
I
2
C Address Bit 1. LVCMOS/LVTTL interface levels.
I
2
C Address Bit 0. LVCMOS/LVTTL interface levels.
Active High Output Enable for Q1, nQ1. LVCMOS/LVTTL interface levels.
0 = Output pins high-impedance
1 = Output switching (default)
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Output supply pins for Q1, nQ1 and Q0, nQ0 outputs. Either 2.5V or 3.3V.
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Pullup
Active High Output Enable for Q0, nQ0. LVCMOS/LVTTL interface levels.
0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition. LVCMOS/LVTTL
interface levels.
Indicates which of the two differential clock inputs is currently selected.
LVCMOS/LVTTL interface levels.
0 = CLK0, nCLK0 differential input pair
1 = CLK1, nCLK1 differential input pair
4
Input
Pulldown
5
6
8, 21, 35
9
10
11, 19,
20, 32
CLK0
nCLK0
V
EE
CLK1
nCLK1
nc
Input
Input
Power
Input
Input
Unused
Pulldown
Pullup/
Pulldown
12
PLL_BYPAS
S
SDATA
SCLK
Input
Pulldown
14
15
I/O
Input
Pullup
Pullup
16
CONFIG
Input
Pulldown
17
18
22
S_A1
S_A0
OE1
Input
Input
Input
Pulldown
Pulldown
Pullup
23, 24
25
26, 27
nQ1, Q1
V
CCO
nQ0, Q0
Output
Power
Output
28
OE0
Input
30
LOCK_IND
Output
31
CLK_ACTIVE
Output
©2016 Integrated Device Technology, Inc.
3
Revision B, May 20, 2016
849N202 Datasheet
Table 1. Pin Descriptions
Number
33, 34
36
Name
LF0, LF1
V
CCA
Input
Power
Type
Description
Connection for external loop filter components.
Analog supply voltage. See Applications section for details on how to connect
this pin.
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL
interface levels.
0 = Device is locked to a valid input reference
1 = Device is not locked to a valid input reference
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.
0 = Input Clock 0 is switching within specifications
1 = Input Clock 0 is out of specification
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.
0 = Input Clock 1 is switching within specifications
1 = Input Clock 1 is out of specification
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.
0 = crystal is switching within specifications
1 = crystal is out of specification
37
HOLDOVER
Output
38
CLK0BAD
Output
39
CLK1BAD
Output
40
XTALBAD
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
4
Revision B, May 20, 2016
849N202 Datasheet
Functional Description
The 849N202 is designed to provide two copies of almost any
desired output frequency within its operating range (0.98 - 1300MHz)
from any input source in the operating range (8kHz - 710MHz). It is
capable of synthesizing frequencies from a crystal or crystal
oscillator source. The output frequency is generated regardless of
the relationship to the input frequency. The output frequency will be
exactly the required frequency in most cases. In most others, it will
only differ from the desired frequency by a few ppb. IDT configuration
software will indicate the frequency error, if any. The 849N202 can
translate the desired output frequency from one of two input clocks.
Again, no relationship is required between the input and output
frequencies in order to translate to the output clock rate. In this
frequency translation mode, a low-bandwidth, jitter attenuation option
is available that makes use of an external fixed-frequency crystal or
crystal oscillator to translate from a noisy input source. If the input
clock is known to be fairly clean or if some modulation on the input
needs to be tracked, then the high-bandwidth frequency translation
mode can be used, without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarm outputs are raised both as
register bits and hard-wired pins in the event of any
out-of-specification conditions arising. Clock switching is supported
in manual, revertive & non-revertive modes.
The 849N202 has two factory-programmed configurations that may
be chosen from as the default operating state after reset. This is
intended to allow the same device to be used in two different
applications without any need for access to the I
2
C registers. These
defaults may be over-written by I
2
C register access at any time, but
those over-written settings will be lost on power-down. Please
contact IDT if a specific set of power-up default settings is desired.
running at 622.08MHz or a (255/237) FEC rate OC-12 module
running at 669.32MHz. The different I/O modules would result in a
different level on the CONFIG pin which would select different divider
ratios within the 849N202 for the two different card configurations.
Access via I
2
C would not be necessary for operation using either of
the internal configurations.
Operating Modes
The 849N202 has three operating modes which are set by the
MODE_SEL[1:0] bits. There are two frequency translator modes -
low bandwidth and high bandwidth and a frequency synthesizer
mode. The device will operate in the same mode regardless of which
configuration is active.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
of the device.
Output Dividers & Supported Output Frequencies
In all 3 operating modes, the output stage behaves the same way, but
different operating frequencies can be specified in the two
configurations.
The internal VCO is capable of operating in a range anywhere from
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
the desired output frequency that results in a VCO operating
frequency within that range. The output divider stage N[10:0] is
limited to selection of integers from 2 to 2046. Please refer to Table 3
for the values of N applicable to the desired output frequency.
Table 3. Output Divider Settings & Frequency Ranges
Register
Setting
Nn[10:0]
0000000000x
00000000010
00000000011
00000000100
00000000101
0000000011x
0000000100x
0000000101x
0000000110x
0000000111x
0000001000x
0000001001x
...
1111111111x
Frequency
Divider
N
2
2
3
4
5
6
8
10
12
14
16
18
Even N
2046
Minimum
f
OUT
(MHz)
997.5
997.5
665
498.75
399
332.5
249.4
199.5
166.3
142.5
124.7
110.8
1995 / N
0.98
Maximum
f
OUT
(MHz)
1300
1300
866.7
650
520
433.3
325
260
216.7
185.7
162.5
144.4
2600 / N
1.27
Configuration Selection
The 849N202 comes with two factory-programmed default
configurations. When the device comes out of power-up reset the
selected configuration is loaded into operating registers. The
849N202 uses the state of the CONFIG pin or CONFIG register bit
(controlled by the CFG_PIN_REG bit) to determine which
configuration is active. When the output frequency is changed either
via the CONFIG pin or via internal registers, the output behavior may
not be predictable during the register writing and output settling
periods. Devices sensitive to glitches or runt pulses may have to be
reset once reconfiguration is complete.
Once the device is out of reset, the contents of the operating registers
can be modified by write access from the I
2
C serial port. Users that
have a custom configuration programmed may not require I
2
C
access.
It is expected that the 849N202 will be used almost exclusively in a
mode where the selected configuration will be used from device
power-up without any changes during operation. For example, the
device may be designed into a communications line card that
supports different I/O modules such as a standard OC-12 module
©2016 Integrated Device Technology, Inc.
5
Revision B, May 20, 2016
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