NB3N1200K, NB3W1200L
3.3 V 100/133 MHz
Differential 1:12 HCSL or
Push-Pull Clock ZDB/Fanout
Buffer for PCle
Description
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The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel
®
QuickPath Interconnect
(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and
Intel Scalable Memory Interconnect (Intel SMI) applications. The
VCO of the device is optimized to support 100 MHz and 133 MHz
frequency operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power
NMOS Push−Pull buffer type.
Features
64
1
QFN64
MN SUFFIX
CASE 485DH
MARKING DIAGRAMS
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12 Differential Clock Output Pairs @ 0.7 V
HCSL Compatible Outputs for NB3N1200K
Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI
Phase Jitter
DB1200Z and DB1200ZL Compliant
3.3 V
±5%
Supply Voltage Operation
Fixed−Feedback for Lowest Input−To−Output Delay Variation
SMBus Programmable Configurations to Allow Multiple Buffers in a
Single Control Network
PLL Bypass Configurable for PLL or Fanout Operation
Programmable PLL Bandwidth
2 Tri−level Addresses Selection (9 SMBUS Addresses)
Individual OE Control Pin for Each of 12 Outputs
50 ps Max Output−to−Output Skew Performance
50 ps Max Cycle−to−Cycle Jitter (PLL mode)
100 ps Input to Output Delay Variation Performance
QFN 64−pin Package, 9 mm x 9 mm
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
0°C to +70°C Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
NB3N
1200K
AWLYYWWG
NB3W
1200L
AWLYYWWG
NB3x1200x= Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
NB3N1200KMNG
NB3N1200KMNTXG
NB3W1200LMNG
NB3W1200LMNTXG
Package
QFN−64
(Pb−Free)
QFN−64
(Pb−Free)
QFN−64
(Pb−Free)
QFN−64
(Pb−Free)
Shipping
†
260 Units /
Tray
1000 / Tape &
Reel
260 Units /
Tray
1000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2017
1
July, 2017 − Rev. 3
Publication Order Number:
NB3N1200K/D
NB3N1200K, NB3W1200L
12
OE_[11:0]#
FB_OUT*
FB_OUT#*
SSC Compatible
PLL
DIF_[11:0]
DIF_[11:0]#
MUX
CLK_IN
CLK_IN#
100M_133M#
HBW_BYPASS_LBW#
SA_0
SA_1
PWRGD/PWRDN#
SDA
SCL
Control
Logic
* FB_OUT pins are for NB3N1200K only; they are NC for NB3W1200L
** IREF pin is for NB3N1200K only; it is NC for NB3W1200L
IREF**
R
REF
Figure 1. Simplified Block Diagram
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2
NB3N1200K, NB3W1200L
PIN CONNECTIONS
DIF_11#
DIF_11
OE_11#
OE_10#
DIF_10#
DIF_10
GND
VDD
VDD
DIF_9#
DIF_9
OE_9#
OE_8#
DIF_8#
DIF_8
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA
GNDA
IREF
100M_133M#
HBW_BYPASS_LBW#
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FB_OUT#
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
Exposed Pad (EP)
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NB3N1200K
(Top View)
GND
DIF_7#
DIF_7
OE_7#
OE_6#
DIF_6#
DIF_6
GND
VDD
DIF_5#
DIF_5
OE_5#
OE_4#
DIF_4#
DIF_4
GND
Figure 2. NB3N1200K Pinout: QFN−64 (Top View)
DIF_11#
DIF_11
OE_11#
OE_10#
DIF_10#
DIF_10
GND
VDD
VDD_IO
DIF_9#
DIF_9
OE_9#
OE_8#
DIF_8#
DIF_8
VDD_IO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DIF_0
DIF_0#
OE_0#
OE_1#
DIF_1
DIF_1#
GND
VDD
VDD
DIF_2
DIF_2#
OE_2#
OE_3#
DIF_3
DIF_3#
VDD
VDDA
GNDA
NC
100M_133M#
HBW_BYPASS_LBW#
PWRGD/PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
Exposed Pad (EP)
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NB3W1200L
(Top View)
GND
DIF_7#
DIF_7
OE_7#
OE_6#
DIF_6#
DIF_6
GND
VDD
DIF_5#
DIF_5
OE_5#
OE_4#
DIF_4#
DIF_4
GND
Figure 3. NB3W1200L Pinout: QFN−64 (Top View)
DIF_0
DIF_0#
OE_0#
OE_1#
DIF_1
DIF_1#
GND
VDD
VDD_IO
DIF_2
DIF_2#
OE_2#
OE_3#
DIF_3
DIF_3#
VDD_IO
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3
NB3N1200K, NB3W1200L
Table 1. NB3N1200K PIN DESCRIPTIONS
Pin Number
1
2
3
Pin Name
VDDA
GNDA
IREF
Type
3.3 V
GND
I
3.3 V Power Supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin to set the differential output current.
Use R
REF
= 475
W,
1% for 100 Ohms trace.
Use R
REF
= 412
W,
1% for 85 Ohms trace.
Input/output Frequency Selection (FS). An external pull−up
or pull−down resistor is attached to this pin to select the input/output frequency.
High = 100 MHz Output
Low = 133 MHz Output
Tri−Level input for selecting the PLL bandwidth or bypass mode
(refer to tri− level threshold in Table 4).
High = High BW mode Med = Bypass mode Low = Low BW mode
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
3.3 V power supply for receiver.
0.7 V Differential True input
0.7 V Differential Complementary input
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
Open collector SMBus data.
SMBus slave clock input.
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
Complementary Feedback out pin, termination required.
See External Feedback Termination section.
True Feedback out pin, termination required.
See External Feedback Termination section.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 0.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 1.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
3.3 V power supply for outputs.
3.3 V power supply for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 2.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 3.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
Ground for outputs.
Description
4
100M_133M#
I, SE
5
HBW_BYPASS_LBW#
I, SE
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PWRGD / PWRDN#
GND
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FB_OUT#
FB_OUT
DIF_0
DIF_0#
OE_0#
OE_1#
DIF_1
DIF_1#
GND
VDD
VDD
DIF_2
DIF_2#
OE_2#
OE_3#
DIF_3
DIF_3#
VDD
GND
I, SE
GND
VDD
I, DIF
I, DIF
I, SE
I/O
I/O
I, SE
O, DIF
O, DIF
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
GND
3.3 V
3.3 V
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
3.3 V
GND
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4
NB3N1200K, NB3W1200L
Table 1. NB3N1200K PIN DESCRIPTIONS
Pin Number
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
EP
Pin Name
DIF_4
DIF_4#
OE_4#
OE_5#
DIF_5
DIF_5#
VDD
GND
DIF_6
DIF_6#
OE_6#
OE_7#
DIF_7
DIF_7#
GND
VDD
DIF_8
DIF_8#
OE_8#
OE_9#
DIF_9
DIF_9#
VDD
VDD
GND
DIF_10
DIF_10#
OE_10#
OE_11#
DIF_11
DIF_11#
Exposed Pad
Type
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
3.3 V
GND
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
GND
3.3 V
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
3.3 V
3.3 V
GND
O, DIF
O, DIF
I, SE
I, SE
O, DIF
O, DIF
Thermal
Description
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 4.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 5.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
Ground for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 6.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 7.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
3.3 V power supply for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 8.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 9.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
3.3 V power supply for outputs.
Ground for outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 10.
0 enables outputs, 1 disables outputs. Internal pull down.
3.3 V LVTTL active low input for enabling DIF output pair 11.
0 enables outputs, 1 disables outputs. Internal pull down.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
The Exposed Pad (EP) on the QFN−64 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die,
and must be electrically and thermally connected to GND on the PC board.
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