Datasheet
Standard EEPROMs
Plug & Play EEPROMs
(for Display)
BR24C21xxx Series (1K)
●General
Description
TM
TM
BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1 /DDC2 interfaces for Plug and Play
displays
●Features
TM
TM
Compatible with both DDC1 /DDC2
Operating voltage range: 2.5V to 5.5V
Page write function: 8bytes
Low power consumption
Active (at 5V)
: 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
Address auto increment function during Read
operation
Data security
Write enable feature (VCLK)
Write protection at low Vcc
Initial data=FFh
Data retention: 10years
Rewriting possible up to 100,000 times
●Packages
W(Typ.) x D(Typ.) x H(Max.)
DIP-T8
9.30mm x 6.50mm x 7.10mm
SOP8
5.00mm x 6.20mm x 1.71mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
●BR24C21xxx
series
Capacity
Type
1Kbit
BR24C21
Power source Voltage
2.5V to 5.5V
DIP-T8
●
SOP8
●
SOP-J8
●
SSOP-B8
●
●Absolute
Maximum Ratings
Parameter
Symbol
Supply Voltage
V
CC
Ratings
-0.3 to +6.5
800(DIP-T8)
450 (SOP8)
450 (SOP-J8)
350(SSOP-B8)
-65 to +125
-40 to +85
-0.3 to Vcc+0.3
Unit
V
Remarks
When using at Ta=25℃ or higher 8.0mW to be reduced per 1℃.
Power Dissipation
Pd
mW
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.5mW to be reduced per 1℃.
Storage Temperature
Operating Temperature
Terminal Voltage
Tstg
Topr
‐
℃
℃
V
●Memory
cell characteristics
Parameter
Write/Erase Cycle
Data Retention
Min.
100,000
10
Limits
Typ.
－
－
Max
－
－
Unit
Times
Years
○Product
structure：Silicon monolithic integrated circuit
.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This
product is not designed protection against radioactive rays
1/18
TSZ02201-0R2R0G100270-1-2
30.Oct.2012 Rev.002
BR24C21xxx Series (1K)
●Recommended
Operating Ratings
Parameter
Symbol
Supply Voltage
V
CC
Input voltage
VIN
Datasheet
Ratings
2.5 to 5.5
0 to Vcc
Unit
V
●Electrical
characteristics
DC (Unless otherwise specified, Ta=-40℃ to +85℃½V
CC
=2.5V to 5.5V)
Parameter
“H” Input Voltage 1
“L” Input Voltage 1
“H” Input Voltage 2
“L” Input Voltage 2
“L” Input Voltage 3
“L” Output Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Symbol
VIH1
VIL1
VIH2
VIL2
VIL3
VOL
ILI
ILO
ICC
ISB
Limits
Min.
0.7V
CC
-
2.0
-
-
-
-1
-1
-
-
Typ.
-
-
-
-
-
-
-
-
-
10
Max.
-
0.3V
CC
-
0.8
0.2V
CC
0.4
1
1
3.0
100
Unit
V
V
V
V
V
V
µA
µA
mA
µA
Condition
SCL, SDA
SCL, SDA
VCLK
VCLK, V
CC
≧4.0V
VCLK, V
CC
＜4.0V
SDA, IOL=3.0mA
SCL, VCLK, VIN=0V to V
CC
SDA, VOUT=0V to V
CC
V
CC
=5.5V, fSCL=400kHz
V
CC
=5.5V, SDA=SCL=V
CC
,VCLK=GND *1
*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the VCLK pin.
After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the operating current flows.
Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.
AC (Unless otherwise specified, Ta=-40℃ to +85℃,V
CC
=2.5V to 5.5V)
Parameter
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time(SCL)
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
Output Data Delay Time(VCLK)
VCLK High Period
VCLK Low Period
VCLK Setup Time
VCLK Hold Time
Mode Transition Time
Transmit-Only Powerup Time
Noise Spike Width (VCLK)
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tSU:STO
tBUF
tWR
tI
tVPD
tVHIGH
tVLOW
tVSU
tVHD
tVHZ
tVPU
tVI
Fast-mode
V
CC
=2.5V to 5.5V
Min.
-
0.6
1.3
-
-
0.6
0.6
0
100
-
0.6
1.3
-
-
-
0.6
1.3
0
0.6
-
0
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
10
0.1
1.0
-
-
-
-
0.5
-
0.1
Standard-mode
V
CC
=2.5V to 5.5V
Min.
-
4.0
4.7
-
-
4.0
4.7
0
250
0.2
4.0
4.7
-
-
-
4.0
4.7
0
4.0
-
0
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
100
-
-
1.0
0.3
-
-
-
-
3.5
-
-
10
0.1
2.0
-
-
-
-
1.0
-
0.1
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
ms
µs
µs
µs
µs
µs
µs
µs
µs
µs
Unit
AC OPERATING CHARACTERISTICS (Transmit-Only Mode)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/18
TSZ02201-0R2R0G100270-1-2
30.Oct.2012 Rev.002
BR24C21xxx Series (1K)
●Block
Diagram
Datasheet
N.C. 1
7bit
1 Kbit
EEPROM
ARRAY
8bit
8
V
CC
N.C. 2
ADDRESS
DECODER
7bit
SLAVE・WORD
ADDRESS REGISTER
DATA
REGISTER
7
VCLK
START
STOP
N.C. 3
CONTROL LOGIC
ACK
6
SCL
GND 4
HIGH VOLTAGE
V
CC
LEVEL DETECT
5
SDA
●Pin
Configuration
(TOP VIEW)
V
CC
VCLK
SCL
SDA
BR24C21
BR24C21F
BR24C21FJ
BR24C21FV
N.C.
N.C.
N.C.
GND
●Pin
Descriptions
Pin Name
V
CC
GND
N.C.
SCL
SDA
VCLK
I/O
-
-
-
IN
IN/OUT
IN
Power Supply
Ground (0V)
No Connection
Functions
Serial Clock Input for Bi-directional Mode
Slave and Word Address,
*1
Serial Data Input, Serial Data Output
Clock Input (Transmit-Only Mode)
Write Enable (Bi-directional Mode)
*1 An open drain output requires a pull-up resistor.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/18
TSZ02201-0R2R0G100270-1-2
30.Oct.2012 Rev.002
BR24C21xxx Series (1K)
●Synchronous
data timing
t
R
t
F
t
HIGH
Datasheet
SCL
t
HD
:STA
t
SU
:DAT
t
LOW
t
HD
:DAT
SCL
SDA
(IN)
t
BUF
t
PD
SDA
D0
WRITE DATA(n)
ACK
t
WR
STOP CONDITION
START CONDITION
SDA
(OUT)
Figure 2.
Write Cycle Timing
START BIT
STOP BIT
SCL
t
SU
:STA
SDA
STOP BIT
tHD:STA
SCL
t
SU
:STO
SDA
START BIT
VCLK
Figure 1. Synchronous Data Timing
・
SDA data is latched into the chip at the rising edge of the SCL clock.
・
Output data toggles at the falling edge of the SCL clock.
t
VSU
WRITE COMMAND
t
VHD
Figure 3.
Write Enable Timing
●Transmit-only
mode
・
After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock
to the VCLK pin.
・
When the power is on, the SCL pin needs to be set to V
CC
(High level).
・
SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After
power on, the output data is as follows:
00h address data
→
01h address data
→
02h address data
→
…
The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Figure 4.)
・
In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Figure 5.)
・
The read operation is in Transmit-Only Mode and can be started after the power is stabilized.
tVHIGH tVLOW
Vcc
VCLK
SCL
1
9
10
tVPD
VCLK
½VPU
SDA
D1
ADDRESS n
DATA
D0
NULL BIT
DATA=1
D7
D6
ADDRESS n+1
DATA
SDA
D7
D6
D5
D4
D3
00h ADDRESS DATA
Figure 4.
Transmit Only Mode
Figure 5.
Null Bit
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111
・
15
・
001
4/18
TSZ02201-0R2R0G100270-1-2
30.Oct.2012 Rev.002
BR24C21xxx Series (1K)
Datasheet
●Bi-directional
mode
○
Bi-directional Mode and Recovery Function
・
The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low
transition at the SCL pin, while the state of SDA is at high-impedance.
・
After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK
counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode
(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal to
Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.
・
If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional
Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only
way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an
Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for
Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,
it is possible to revert to Transmit-Only Mode.
・
When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.
Tra nsm it -o nl y
Tra nsm it - On l y
Tra nsm it -o nl y
Ｍ Ｄ Transmit-only
ＯＥ
Bi-directional
Bi-directional
T r a
Transition Mode
d e w i t h p o s s i b i l i t y
n s i t i o n M o
with possibility to
t o r
return to Transmit-Only Mode
O n l y M o d e
e tu ne to Tra nsmit -
Transmit-Only
Transmit-oOnly
ＭＤ
ＯＥ
Bi-directional
Bi-directional
T r a n s i t i o n M o d
possibility to
s s i b i l i t y
Transition Mode with
e w i t h p o
t
return
t
to
n e t o T r a n
Mode
i t - O n l y M o d e
o r e u
Transmit-Only
s m
Bi-directional
Bi-directional
p a r m
parmanently
anently
１
ＶＬ
ＣＫ
２
３
４
２
１７ １８ １９
２ ２
ＶＬ
ＣＫ
１
２
½１８
＜２
½
ＳＬ
Ｃ
½Ｈ
ＶＺ
ADDRESS 00h
ADDRESS 00h
ＳＬ
Ｃ
½Ｈ
ＶＺ
Ｄ Ｄ Ｄ Ｄ
７ ６ ５ ４
ＳＡ
Ｄ
ＳＡ
Ｄ
Ｓ
１
０
１
０
＊
＊
Ｃ
＊ Ｒ/Ｗ Ａ Ｋ
*Don’t
care
Figure 6. Recovery Mode
Figure 7. Mode Change
○
Bi-directional Mode
START Condition
・
All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.
・
The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to
any commands until this condition has been met.
(See Figure 1 Synchronous Data Timing)
STOP Condition
・
All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.
・
The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.
・
The STOP condition is also used to place the device into standby power mode after read sequences.
・
A STOP condition can only be issued after the transmitting device has released the bus.
(See Figure 1 Synchronous Data Timing)
Device Addressing
・
Following the START condition, the Master outputs the device address of the Slave to be accessed. The most significant
four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as “1010.”
・
The next three bits of the slave address are inconsequential.
・
The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.
When set to “0”, a WRITE operation is initiated.
R/W set to "0"
・ ・ ・ ・ ・ ・ ・ ・
WRITE (This bit is also set to "0" for random read operation)
R/W set to "1"
・ ・ ・ ・ ・ ・ ・ ・
READ
1010
＊
＊
＊
_
R/W
＊：
Don’t care
○
Write Protect Function
・
Write Enable (VCLK)
When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting VCLK
High allows normal write operations, while setting VCLK low prevents writing to any location in the array.
(See Figure 3 Write Enable Timing)
Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111
・
15
・
001
5/18
TSZ02201-0R2R0G100270-1-2
30.Oct.2012 Rev.002
微控制器 MCU
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