74LV164
8-bit serial-in/parallel-out shift register
Rev. 4 — 9 December 2015
Product data sheet
1. General description
The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible
with the 74HC164 and 74HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output
from each of the eight stages. Data is entered serially through one of two inputs (DSA or
DSB) and either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into Q0, which is the logical AND-function of the two data inputs (DSA and
DSB) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce): < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot): > 2 V at V
CC
= 3.3 V and T
amb
= 25
C
Gated serial data inputs
Asynchronous master reset
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +80
C
and from
40 C
to +125
C.
NXP Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV164D
74LV164DB
74LV164PW
74LV164BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LV164
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 9 December 2015
2 of 18
NXP Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4.
Pin configuration SO14, SSOP14 and
TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0
Q1
Q2
Q3
GND
CP
MR
Q4
Q5
Q6
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input SA
data input SB
output 0
output 1
output 2
output 3
ground (0 V)
clock input (edge triggered LOW-to-HIGH)
master reset input (active LOW)
output 4
output 5
output 6
output 7
supply voltage
74LV164
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 9 December 2015
3 of 18
NXP Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
6. Functional description
6.1 Function table
Table 3.
Function table
[1]
Input
MR
Reset (clear)
Shift
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition.
Operating mode
Output
CP
X
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14 package
(T)SSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
[2]
[3]
[4]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
-
Max
+7.0
20
50
25
50
-
+150
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74LV164
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 9 December 2015
4 of 18
NXP Semiconductors
74LV164
8-bit serial-in/parallel-out shift register
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.2 V
I
O
=
100 A;
V
CC
= 2.0 V
I
O
=
100 A;
V
CC
= 2.7 V
I
O
=
100 A;
V
CC
= 3.0 V
I
O
=
100 A;
V
CC
= 4.5 V
I
O
=
6
mA; V
CC
= 3.0 V
I
O
=
12
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
40 C
to +85
C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
40 C
to +125
C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
0.3V
CC
V
74LV164
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 9 December 2015
5 of 18
嵌入式系统
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