19-1498; Rev 1; 12/99
IT
TION K
VALUA
E
BLE
AVAILA
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
General Description
The MAX3890 serializer is ideal for converting 16-bit-
wide, 155Mbps parallel data to 2.5Gbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers positive-referenced emitter-coupled logic (PECL)
serial data and clock outputs. A fully integrated phase-
locked loop (PLL) synthesizes an internal 2.5GHz serial
clock from a 155.52MHz, 77.76MHz, 51.84MHz, or
38.88MHz reference clock. A loopback data output is
provided to facilitate system diagnostic testing.
The MAX3890 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP exposed-pad
(EP) package.
o
Single +3.3V Supply
o
495mW Power Consumption
o
Exceeds ANSI, ITU, and Bellcore Specifications
o
155Mbps (16-bit wide) Parallel to 2.5Gbps Serial
Conversion
o
Clock Synthesis for 2.5Gbps
o
Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
o
LVDS Parallel Clock and Data Inputs
o
Additional High-Speed Output for System
Loopback Testing
Features
MAX3890
Applications
2.5Gbps SDH/SONET Transmission Systems
2.5Gbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross-Connects
ATM Backplanes
PART
MAX3890ECB
*EP
= Exposed pad
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
155MHz REF CLOCK INPUT
+3.3V
+3.3V
TTL
+3.3V
130Ω
130Ω
V
CC
82Ω
82Ω
+3.3V
PDI0+ RCLK+ RCLK- CLKSET
PDI0-
PDI15+
OVERHEAD
GENERATION
PDI15-
PCLKI+
PCLKI-
PCLKO+
PCLKO-
GND
V
CC
SOS
SDO+
SDO-
MAX3890
130Ω
SCLKO+
SCLKO-
FIL+
FIL-
SLBO+ SLBO-
82Ω
82Ω
130Ω
MAX3867
330nF
OPTIONAL CONNECTION TO MAX3880
FOR SYSTEM LOOPBACK TESTING.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z
0
= 50Ω).
________________________________________________________________
Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3890
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
V
CC
.......................................................................-0.5V to +5V
All Inputs, FIL+, FIL- ...............................-0.5V to (V
CC
+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SDO±, SCLKO±)....................................50mA
CML Outputs (SLBO±)....................................................15mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP-EP (derate 44.8mW/°C above +85°C) ......................1W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), CML loads = 50Ω ±1% to V
CC
,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
PECL OUTPUTS
(SDO±, SCLKO±)
T
A
= 0°C to +85°C
T
A
= -40°C
T
A
= 0°C to +85°C
Output Voltage Low
V
OL
T
A
= -40°C
LVDS INPUTS AND OUTPUTS
(PCLKO±, PDI_±, PCLKI±, RCLKI±)
Input Voltage Range
V
I
Differential input voltage = 100mV
Differential Input Threshold
V
IDTH
Threshold Hysteresis
V
HYST
Differential Input Resistance
R
IN
Output Voltage High
V
OH
Output Voltage Low
V
OL
|V
OD
|
Differential Output Voltage
Figure 5
Output Voltage High
V
OH
Change in Magnitude of Differential
Output Voltage for Complementary
States
Output Offset Voltage
Change in Magnitude of Output Offset
Voltage for Complementary States
Single-Ended Output Resistance
Change in Magnitude of Single-Ended
Output Resistance for Complementary
Outputs
∆|V
OD
|
V
OS
∆V
OS
R
O
∆R
O
40
95
±2.5
1.125
V
CC
- 1.025
V
CC
- 1.085
V
CC
- 1.81
V
CC
-1.83
0
-100
85
0.925
250
60
100
V
CC
- 0.88
V
CC
- 0.88
V
CC
- 1.62
V
CC
- 1.555
2.4
100
115
1.475
400
±25
1.275
±25
140
±10
V
V
SYMBOL
I
CC
CONDITIONS
PECL outputs unterminated,
SOS = low
MIN
TYP
150
MAX
230
UNITS
mA
V
mV
mV
Ω
V
V
mV
mV
V
mV
Ω
%
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), CML loads = 50Ω ±1% to V
CC,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
PROGRAMMING INPUT
(CLKSET)
CLKSET Input Current
TTL INPUT
(SOS)
Input Voltage High
Input Voltage Low
Input Current High
Input Current Low
Differential Output Voltage
Single-Ended Output Resistance
V
IH
V
IL
I
IH
I
IL
|V
OD
|
R
O
-10
-10
100
50
2.0
0.8
10
10
400
V
V
µA
µA
mV
Ω
I
CLKSET
CLKSET = 0 or V
CC
±500
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3890
CURRENT MODE LOGIC (CML) OUTPUTS
(SLBO±)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), CML loads = 50Ω ±1% to V
CC
,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Serial Clock Rate
Parallel Data Setup Time
Parallel Data-Hold Time
PCLKO to PCLKI Skew
Output Jitter Generation (SCLKO±)
PECL Differential Output Rise/Fall
Time
Parallel Input Clock Rate
Reference Clock Input (RCLKI)
Rise/Fall Time
Parallel Clock Output (PCLKO)
Rise/Fall Time
Serial Clock Output (SCLKO) to
Serial-Data Output (SDO) Delay
SYMBOL
f
SCLK
t
SU
t
H
t
SKEW
Φ
0
t
R,
t
F
f
PCLKI
t
R
,
t
F
t
R
,
t
F
t
SCLK-SD
20% to 80%, f = 155.52MHz
20% to 80%
SCLKO rising edge to SDO edge
110
CONDITIONS
(Note 2)
(Note 2)
Figure 2
Jitter bandwidth = 12kHz to 20MHz,
RCLK amplitude >
|
V
IDTH
|
(Note 3)
20% to 80%
155.52
1.0
1.0
290
MIN
300
700
0
TYP
2.488
MAX
UNITS
GHz
ps
ps
ns
ps
RMS
ps
MHz
ns
ns
ps
+4.0
3
120
Note 1:
AC characteristics guaranteed by design and characterization.
Note 2:
Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel
clock with rise/fall time = 1ns (20% to 80%). See Figure 2.
Note 3:
For f
RCLK
= 38.88MHz, the minimum reference clock amplitude is
≥
200mV.
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3890
Typical Operating Characteristics
(V
CC
= +3.3V, PECL loads = 50Ω ±1%, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3890-01
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3890-02
200
180
SUPPLY CURRENT (mA)
160
140
120
PECL OUTPUTS UNTERMINATED
100
-50
-25
0
25
50
75
100
50ps/div
TEMPERATURE (°C)
SERIAL-DATA OUTPUT JITTER
f
RCK
= 155.52MHz
MAX3890-03
OUTPUT JITTER GENERATION
vs. RCLK AMPLITUDE
MAX3890 toc04
3.0
OUTPUT JITTER GENERATION (ps)
2.5
2.0
1.5
1.0
0.5
0
f
RCLK
= 38.88MHz
f
RCLK
= 51.84MHz
f
RCK
= 155.52MHz
f
RCLK
= 155.52MHz
100
150
200
250
f
RCLK
= 77.76MHz
300
350
400
5ps/div
TOTAL WIDEBAND RMS JITTER = 2.155ps
PEAK-TO-PEAK JITTER = 15.7ps
RCLK AMPLITUDE (mV)
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
Pin Description
PIN
1, 17, 33, 48, 49, 63
2, 5, 7, 10, 13,
14, 32, 56, 60, 64
3
4
6
8
9
11
12
15
16
18, 20, 22, 24, 26,
28, 30, 34, 36, 38,
40, 42, 44, 46, 50, 52
19, 21, 23, 25, 27,
29, 31, 35, 37, 39,
41, 43, 45, 47, 51, 53
54
55
57
58
NAME
GND
V
CC
SLBO-
SLBO+
SOS
SCLKO-
SCLKO+
SDO-
SDO+
PCLKI+
PCLKI-
PDI15+ to
PDI0+
Ground
+3.3V Supply Voltage
System Loopback Inverting Output. Enabled when SOS is high.
System Loopback Noninverting Output. Enabled when SOS is high.
System Loopback Output Select. System loopback disabled when low.
Inverting PECL Serial Clock Output
Noninverting PECL Serial Clock Output
Inverting PECL Serial-Data Output
Noninverting PECL Serial-Data Output
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
FUNCTION
MAX3890
PDI15- to
PDI0-
PCLKO+
PCLKO-
RCLK+
RCLK-
Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the
overhead management circuit.
Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the over-
head management circuit.
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal refer-
ence clock to the RCLK inputs.
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference
clock to the RCLK inputs.
Reference Clock Rate Programming Pin:
CLKSET = V
CC
: Reference Clock Rate = 155.52MHz
CLKSET = Open: Reference Clock Rate = 77.76MHz
CLKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz
CLKSET = GND: Reference Clock Rate = 38.88MHz
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
Ground. This must be soldered to a circuit board for proper thermal performance (see
Package Information).
59
CLKSET
61
62
EP
FIL-
FIL+
Exposed
Pad
_______________________________________________________________________________________
5
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