INTEGRATED CIRCUITS
74F112
Dual J-K negative edge-triggered flip-flop
Product specification
IC15 Data Handbook
1990 Feb 09
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
FEATURE
•
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPE
74F112
TYPICAL PROPAGATION DELAY
100MHz
PIN CONFIGURATION
CP0
K0
J0
SD0
Q0
Q0
Q1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RD0
RD1
CP1
K1
J1
SD1
Q1
SF00103
TYPICAL SUPPLY CURRENT (TOTAL)
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F112N
N74F112D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F112N
I74F112D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
J0, J1
K0, K1
SD0, SD1
RD0, RD1
CP0, CP1
Q0, Q0; Q1, Q1
J inputs
K inputs
Set inputs (active Low)
Reset inputs (active Low)
Clock Pulse input (active falling edge)
Data outputs
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/5.0
1.0/5.0
1.0/4.0
50/33
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/3.0mA
20µA/3.0mA
20µA/2.4mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
February 9, 1990
2
853–0338 98775
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
LOGIC SYMBOL
3
11
2 12
IEC/IEEE SYMBOL
3
1
1J
C1
1K
R
S
6
5
1
4
15
13
10
14
J0
CP0
SD0
RD0
CP1
J1
K0 K1
2
15
4
11
SD1
RD1
Q0 Q0 Q1 Q1
13
12
14
10
V
CC
= Pin 16
GND = Pin 8
5
6
9
7
2J
C2
2K
R
S
7
9
SF00104
SF00105
LOGIC DIAGRAM
5, 9
Qn
6, 7
Qn
4, 10
SDn
2, 12
Kn
15, 14
RDn
3, 11
Jn
V
CC
= Pin 16
GND = Pin 8
1, 13
CPn
SF00106
FUNCTION TABLE
INPUTS
SD
L
H
L
H
H
H
H
H
RD
H
L
L
H
H
H
H
H
CP
X
X
X
↓
↓
↓
↓
H
J
X
X
X
h
l
h
l
X
K
X
X
X
h
h
l
l
X
OUTPUTS
Q
H
L
H*
q
L
H
q
Q
Q
L
H
H*
q
H
L
q
Q
Asynchronous Set
Asynchronous Reset
Undetermined *
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold “no change”
Hold “no change”
OPERATING MODE
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓
= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
February 9, 1990
3
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Commercial range
Operating free-air temperature range
free air
Storage temperature range
Industrial range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Commercial range
Operating free-air temperature range
free air
Industrial range
0
–40
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
+85
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Jn, Kn
I
IL
I
OS
Low-level input current
Short-circuit output current
3
CPn
SDn, RDn
V
CC
= MAX
–60
V
CC
= MAX, V
I
= 0.5V
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.5
2.7
3.4
0.35
0.35
–0.73
0.50
0.50
–1.2
100
20
–0.6
–2.4
–3.0
–150
V
µA
µA
mA
mA
mA
mA
V
TYP
2
MAX
UNIT
V
O
OH
High-level
High level output voltage
V
V
O
OL
V
IK
I
I
I
IH
I
CC
Supply current (total)
4
V
CC
= MAX
15
21
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.
February 9, 1990
4
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74F112
AC ELECTRICAL CHARACTERISTICS
LIMITS
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF
R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn or Qn
Propagation delay
SDn, RD to Qn or Qn
Waveform 1
Waveform 1
Waveform 2,3
85
2.0
2.0
2.0
2.0
TYP
100
5.0
5.0
4.5
4.5
6.5
6.5
6.5
6.5
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF
R
L
= 500Ω
MIN
80
2.0
2.0
2.0
2.0
7.5
7.5
7.5
7.5
MAX
V
CC
= +5.0V
±
10%
T
amb
= –40°C to +85°C
C
L
= 50pF
R
L
= 500Ω
MIN
80
2.0
2.0
1.5
1.5
7.5
7.5
7.5
7.5
MAX
MHz
ns
ns
SYMBOL
PARAMETER
UNIT
AC SETUP REQUIREMENTS
LIMITS
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF
R
L
= 500Ω
MIN
t
S
(H)
t
S
((L)
t
h
(H)
t
h
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup time, High or Low
Jn, Kn to CP
Hold time, High or Low
Jn, Kn to CP
CP Pulse width
High or Low
SDn, RD Pulse width
Low
Recovery time
SDn, RD to CP
Waveform 1
Waveform 1
Waveform 1
Waveform 2,3
Waveform 2,3
4.0
3.5
0.0
0.0
4.5
4.5
4.5
4.5
TYP
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF
R
L
= 500Ω
MIN
5.0
4.0
0.0
0.0
5.0
5.0
5.0
5.0
MAX
V
CC
= +5.0V
±
10%
T
amb
= –40°C to +85°C
C
L
= 50pF
R
L
= 500Ω
MIN
5.0
4.0
0.0
0.0
5.0
5.0
5.0
5.0
MAX
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
Jn, Kn
V
M
t
s
(L)
V
M
t
h
(L)
f
max
CPn
V
M
t
w
(L)
V
M
t
w
(H)
t
PLH
Qn
V
M
t
PHL
Qn
V
M
V
M
t
PHL
V
M
t
s
(H)
V
M
t
h
(H)
V
M
t
PLH
V
M
SF00107
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
February 9, 1990
5
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