20A Integrated PowIRstage
®
IR3742
FEATURES
Single input voltage range from 5V to 21V
Wide input voltage range from 1.0V to 21V with
external V
CC
bias voltage
Integrated MOSFET drivers, Control FET,
Synchronous FET with Schottky diode,
bootstrap diode and the internal LDO
Enable input with voltage monitoring capability
Logic Level Tri-state PWM input
Thermally compensated Over Current Indicator
Open-drain over temperature and over current
fault indication
Under-voltage Lockout of VCC/LDO_Out
Operating temp: -40°C < T
j
< 125°C
Package size: 5mm x 6mm PQFN
RoHS6 Compliant, lead-free and halogen-free
DESCRIPTION
The IR3742 integrated PowIRstage
®
is a synchronous
buck gate driver IC with co-packed control and
synchronous MOSFETs and Schottky diode. It is
optimized internally for PCB layout, heat transfer and
driver/MOSFET timing. Custom designed gate driver
and MOSFET combination enables higher efficiency at
lower output voltages required by cutting edge ASIC,
FPGA and advanced controller.
Up to 1.5MHz switching frequency enables high
performance
transient
response,
allowing
miniaturization of output inductors, as well as input and
output capacitors while maintaining industry leading
efficiency. The IR3742’s superior efficiency enables
smallest size and lower solution cost.
The IR3742 includes an over current indicator and over
temperature indicator in the event of a fault condition.
APPLICATIONS
Computing Applications
Set Top Box Applications
Storage Applications
Data Center Applications
Distributed Point of Load Power Architectures
ORDERING INFORMATION
Base Part Number
IR3742
Package Type
PQFN 5 mm x 6 mm
Standard Pack
Form
Quantity
Tape and Reel
4000
Orderable Part Number
IR3742MTRPBF
IR3742
PBF
TR
M
Lead Free
Tape and Reel
Package Type
1
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March 12, 2014
IR3742
BASIC APPLICATION
Vin
Vin PVin
Enable
IR3742
PWM
OC_En
NC Gnd
Vcc /
LDO_out
Fault
PGnd
VCC
Fault
Boot
SW
Vo
92
Efficiency [%]
90
88
86
84
82
80
78
0
5
10
Iout [A]
15
20
Figure 1: IR3742 Basic Application Circuit
Figure 2: IR3742 Efficiency –
PVin=Vin=12V, Vout=1.2V, Fs=300kHz, L=470nH
[DCR=0.165mOhm]
PINOUT DIAGRAM
Figure 3: 5mm x 6mm PQFN (Top View)
2
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IR3742
BLOCK DIAGRAM
10
Vcc/ LDO_Out
Vin
9
6.8V Internal
LDO
VCC
14
Boot
UVcc
3.3V
UVcc
5.1kΩ
13
PWM
6
5.1kΩ
HDrv
PVin
Gnd
4
PWM LOGIC
and
DEAD-TIME
CONTROL
DRIVER
Gnd
17
12
VCC
SW
UVcc
POR
LDrv
DRIVER
Enable
15
UVEN
POR
TSD
11
PGnd
Fault
7
Q
R
FAULT
FAULT
THERMAL FAULT
DETECTION
100kΩ
3.3V
CONTROL
S
OC
OVER CURRENT
DETECTION
5
OC_En
Figure 4: Simplified Block Diagram
3
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IR3742
PIN DESCRIPTIONS
PIN #
1, 2, 3, 8,
16
4, 17
5
6
PIN NAME
PIN DESCRIPTION
NC
Gnd
OC_En
PWM
Must be connected to signal ground on the PCB layout.
Signal ground for internal reference and control circuitry.
Over current detection enable pin. Floating this pin enables the over current detection.
Shorting this pin to GND disables the over current detection.
Logic level tri-state PWM input. “High” turns the control MOSFET on, and “Low” turns the
synchronous MOSFET on. “Tri-state” turns both MOSFETs off.
Open-drain fault indication. Connect a pull-up resistor from this pin to Vcc. Fault pin stays
high when VCC/LDO_Out or Enable voltage is below their thresholds. In normal
operation, Fault pin stays high. When over temperature or over current occurs, Fault pin is
latched low. Recycle Vcc or Enable to reset.
Input for internal LDO. A 1.0µF capacitor should be connected between this pin and
PGnd. If an external supply is connected to Vcc/LDO_out pin, this pin should be shorted
to Vcc/LDO_out pin.
Output of the internal LDO and optional input of an external biased supply voltage. A
minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd.
Power Ground. This pin serves as a separated ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
Switch node. Connect this pin to the output inductor.
Input voltage for power stage.
Supply voltage for high side driver, a 100nF capacitor should be connected between this
pin and SW pin.
Enable pin to turn on and off the device. Input voltage monitoring (input UVLO) can also
be implemented by connecting this pin to PVin pin through a resistor divider.
7
Fault
9
V
in
10
11
12
13
14
15
Vcc/LDO_Out
PGnd
SW
PV
in
Boot
Enable
4
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March 12, 2014
IR3742
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin to PGnd (Note 4)
Vcc/LDO_Out to PGnd (Note 4)
Boot to PGnd (Note 4)
SW to PGnd (Note 4)
Boot to SW
Fault to Gnd (Note 4)
PWM, to Gnd
Enable, OC_En to Gnd (Note 4)
PGnd to Gnd
THERMAL INFORMATION
Junction to Ambient Thermal Resistance Ɵ
jA
Junction to PCB Thermal Resistance Ɵ
j-PCB
Storage Temperature Range
Junction Temperature Range
30 °C/W (Note 3)
2 °C/W
-55°C to 150°C
-40°C to 150°C
-0.3V to 25V
-0.3V to 8V (Note 1)
-0.3V to 33V
-0.3V to 25V (DC), -V
CC
for 20ns (AC)
-0.3V to V
CC
+ 0.3V (Note 2)
-0.3V to V
CC
+ 0.3V (Note 2)
-0.3V to 5V
-0.3V to +3.9V
-0.3V to +0.3V
Note 1:
Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
Note 2:
Must not exceed 8V.
Note 3:
Based on a 4-layer PCB board (2.23”x2”) using 2 oz. copper on each layer.
Note 4:
PGnd pin and Gnd pin are connected together.
5
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March 12, 2014
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