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74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 5 — 17 March 2016
Product data sheet
1. General description
The 74LV4052 is a low-voltage CMOS device and is pin and function compatible with the
74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer with a common select
logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common
input/output (nZ). The common channel select logics include two digital select inputs (S0
and S1) and an active LOW enable input (E). With E LOW, one of the four switches is
selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the
high impedance OFF-state, independent of S0 and S1. V
CC
and GND are the supply
voltage pins for the digital control inputs (S0, S1 and E). The V
CC
to GND ranges are 1.0 V
to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between V
CC
as a
positive limit and V
EE
as a negative limit. V
CC
- V
EE
may not exceed 6.0 V. For operation
as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically ground).
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 6.0 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low ON resistance:
145
(typical) at V
CC
V
EE
= 2.0 V
90
(typical) at V
CC
V
EE
= 3.0 V
60
(typical) at V
CC
V
EE
= 4.5 V
Logic level translation:
To enable 3 V logic to communicate with
3
V analog signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV4052D
74LV4052DB
74LV4052PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
Fig 1.
Functional diagram
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 17 March 2016
2 of 25
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Schematic diagram (one switch)
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 17 March 2016
3 of 25
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration for SO16 and (T)SSOP16
5.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
S1
S0
1Y3
1Y0
1Z
1Y1
1Y2
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input
select logic input
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
positive supply voltage
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 17 March 2016
4 of 25
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