CAT93C46R
1 kb Microwire Serial
EEPROM
Description
The CAT93C46R is a 1 kb CMOS Serial EEPROM device which is
organized as either 64 registers of 16 bits or 128 registers of 8 bits, as
determined by the state of the ORG pin. The CAT93C46R features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
In contrast to the CAT93C46, the CAT93C46R features an internal
instruction clock counter which provides improved noise immunity
for Write/Erase commands.
Features
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PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 4 MHz @ 5 V, 2 MHz @ 1.8 V
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
V
CC
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8**
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
CS
SK
DI
DO
1
V
CC
NC
ORG
GND
PDIP (L), SOIC (V),
TSSOP (Y), TDFN (VP2)**
(Top View)
** Not recommended for new designs
PIN FUNCTION
Pin Name
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
CS
ORG
CS
SK
DI
CAT93C46R
DO
SK
DI
DO
V
CC
GND
GND
ORG
NC
Figure 1. Functional Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Note: When the ORG pin is connected to V
CC
, the
x16 organization is selected. When it is connected
to ground, the x8 pin is selected. If the ORG pin is
left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 9
1
Publication Order Number:
CAT93C46R/D
CAT93C46R
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Value
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, T
A
= 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V, unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current (Standby) (x8 Mode)
Power Supply Current (Standby) (x16 Mode)
Input Leakage Current
Output Leakage Current (Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1 MHz
V
CC
= 5.0 V
f
SK
= 1 MHz
V
CC
= 5.0 V
CS = 0 V
ORG = GND
CS = 0 V
ORG = Float or V
CC
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
,
CS = 0 V
4.5 V
v
V
CC
< 5.5 V
4.5 V
v
V
CC
< 5.5 V
1.8 V
v
V
CC
< 4.5 V
1.8 V
v
V
CC
< 4.5 V
4.5 V
v
V
CC
< 5.5 V
I
OL
= 2.1 mA
4.5 V
v
V
CC
< 5.5 V
I
OH
=
−400
mA
1.8 V
v
V
CC
< 4.5 V
I
OL
= 1 mA
1.8 V
v
V
CC
< 4.5 V
I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
−0.1
2
0
V
CC
x 0.7
Min
Max
1
500
10
10
2
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
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CAT93C46R
Table 4. PIN CAPACITANCE
Symbol
C
OUT
(Note 4)
C
IN
(Note 4)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS
(Note 5)
V
CC
= 1.8 V
−
5.5 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 6)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2
DC
Parameter
Min
50
0
100
100
0.25
0.25
100
5
0.1
0.1
0.1
0.1
4
Max
V
CC
= 4.5 V
−
5.5 V
Min
50
0
50
50
0.1
0.1
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
MHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. POWER−UP TIMING
(Notes 4 and 7)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
v
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
v
V
CC
v
5.5 V
4.5 V
v
V
CC
v
5.5 V
1.8 V
v
V
CC
v
4.5 V
1.8 V
v
V
CC
v
4.5 V
Current Source I
OLmax
/I
OHmax
; C
L
= 100 pF
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CAT93C46R
Table 8. INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
A6−A0
A6−A0
A6−A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
x16
A5−A0
A5−A0
A5−A0
11XXXX
00XXXX
10XXXX
01XXXX
D7−D0
D15−D0
D7−D0
D15−D0
x8
Data
x16
Comments
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
Device Operation
The CAT93C46R is a 1024−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C46R can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 9−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10−bit instructions control the reading, writing and erase
operations of the device. The CAT93C46R operates on a
single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organization).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
Sequential Read
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS is
continuously asserted and SK continues to toggle, the device
will keep incrementing to the next address automatically
until it reaches the end of the address space, then loops back
to address 0. In the sequential Read mode, only the initial
data word is preceeded by a dummy zero bit; all subsequent
data words will follow without a dummy zero bit.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power−up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device is
removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status.
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CAT93C46R
t
SKHI
SK
t
DIS
DI
t
CSS
CS
t
DIS
DO
t
PD0
, t
PD1
DATA VALID
t
CSMIN
VALID
VALID
t
DIH
t
SKLOW
t
CSH
Figure 2. Synchronous Data Timing
SK
t
CSMIN
CS
A
N
DI
1
1
0
t
HZ
0
D
N
D
N−1
D
1
D
0
HIGH−Z
A
N−1
A
0
STANDBY
DO
HIGH−Z
t
PD0
Figure 3. Read Instruction Timing
SK
1
CS
A
N
DI
1
1
0
A
N−1
A
0
Don’t Care
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DO
HIGH−Z
Dummy 0
D
15
...D
0
or
D
7
...D
0
Address + 1
D
15
...D
0
or
D
7
...D
0
Address + 2
D
15
...D
0
or
D
7
...D
0
Address + n
D
15
...
or
D
7
...
Figure 4. Sequential Read Instruction Timing
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