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Logic-Level Gate Drive
Advanced Process Technology
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Surface Mount (IRLZ34NS)
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Low-profile through-hole (IRLZ34NL)
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175°C Operating Temperature
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Fast Switching
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Fully Avalanche Rated
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Lead-Free
Description
HEXFET Power MOSFET
D
IRLZ34NSPbF
IRLZ34NLPbF
®
V
DSS
= 55V
R
DS(on)
= 0.035Ω
PD - 95583
G
I
D
= 30A
S
Absolute Maximum Ratings
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRLZ34NL) is available for low-
profile applications.
D 2 Pak
TO-262
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
30
21
110
3.8
68
0.45
±16
110
16
6.8
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
2.2
40
Units
°C/W
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1
07/20/04
IRLZ34NS/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
V
(BR)DSS
Drain-to-Source Breakdown Voltage
∆V
(BR)DSS
/∆T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min.
55
1.0
11
Typ.
0.065
8.9
100
21
29
Max. Units
Conditions
V
V
GS
= 0V, I
D
= 250µA
V/°C Reference to 25°C, I
D
= 1mA
0.035
V
GS
= 10V, I
D
= 16A
0.046
Ω
V
GS
= 5.0V, I
D
= 16A
0.060
V
GS
= 4.0V, I
D
= 14A
2.0
V
V
DS
= V
GS
, I
D
= 250µA
S
V
DS
= 25V, I
D
= 16A
25
V
DS
= 55V, V
GS
= 0V
µA
250
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 16V
nA
-100
V
GS
= -16V
25
I
D
= 16A
5.2
nC V
DS
= 44V
14
V
GS
= 5.0V, See Fig. 6 and 13
V
DD
= 28V
I
D
= 16A
ns
R
G
= 6.5Ω, V
GS
= 5.0V
R
D
= 1.8Ω, See Fig. 10
Between lead,
7.5
nH
and center of die contact
880
V
GS
= 0V
220
pF
V
DS
= 25V
94
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Min. Typ. Max. Units
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Conditions
D
MOSFET symbol
30
showing the
A
G
integral reverse
110
S
p-n junction diode.
1.3
V
T
J
= 25°C, I
S
= 16A, V
GS
= 0V
76 110
ns
T
J
= 25°C, I
F
= 16A
190 290
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
R
G
= 25Ω, I
AS
= 16A. (See Figure 12)
I
SD
≤
16A, di/dt
≤
270A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
V
DD
= 25V, starting T
J
= 25°C, L =610µH
Pulse width
≤
300µs; duty cycle
≤
2%.
Uses IRLZ34N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRLZ34NS/LPbF
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
1000
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
10
10
2.5V
1
1
2.5V
0.1
0.1
20µs PULSE WIDTH
T
J
= 25°C
1
10
A
100
0.1
0.1
20µs PULSE WIDTH
T
J
= 175°C
1
10
A
100
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
1000
3.0
I
D
= 27A
I
D
, Drain-to-Source Current (A)
2.5
100
T
J
= 25°C
T
J
= 175°C
10
2.0
1.5
1.0
1
0.5
0.1
2
3
4
5
6
V
DS
= 25V
20µs PULSE WIDTH
7
8
9
10
A
0.0
-60 -40 -20
0
20
40
60
V
GS
= 10V
80 100 120 140 160 180
A
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRLZ34NS/LPbF
1400
V
GS
, Gate-to-Source Voltage (V)
1200
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
iss
C
oss
= C
ds
+ C
gd
15
I
D
= 16A
V
DS
= 44V
V
DS
= 28V
12
C, Capacitance (pF)
1000
800
9
C
oss
600
6
400
C
rss
200
3
0
1
10
100
A
0
0
4
8
12
16
FOR TEST CIRCUIT
SEE FIGURE 13
20
24
28
32
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
I
D
, Drain Current (A)
100
10µs
T
J
= 175°C
T
J
= 25°C
10
100µs
10
1ms
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
GS
= 0V
1.8
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
10ms
2.0
A
100
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRLZ34NS/LPbF
40
V
DS
V
GS
R
D
I
D
, Drain Current (A)
30
R
G
5.0V
D.U.T.
+
V
DD
-
20
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
10
V
DS
90%
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( °C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.20
0.10
0.05
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
0.1
0.02
0.01
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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