19-2710; Rev 4; 7/06
KIT
ATION
EVALU
BLE
AVAILA
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
Features
♦
2.488Gbps and 2.667Gbps Input Data Rates
♦
Reference Clock Not Required for Data
Acquisition
♦
Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
♦
2.7mUI
RMS
Clock Jitter Generation
♦
10mV
P-P
Input Sensitivity Without Threshold
Adjust
♦
0.65UI
P-P
High-Frequency Jitter Tolerance
♦
±170mV Wide Input Threshold Adjust Range
♦
Clock Holdover Capability Using Frequency-
Selectable Reference Clock
♦
Serial Loopback Input Available for System
Diagnostic Testing
♦
Loss-of-Lock (LOL) Indicator
♦
Small 5mm
✕
5mm 32-Pin QFN Package
General Description
The MAX3874 is a compact, dual-rate clock and data
recovery with limiting amplifier for OC-48 and OC-48
with FEC SONET/SDH applications. Without using an
external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by this recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system-loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain
a valid clock output in the absence of data transitions.
The device also includes a loss-of-lock (LOL) output.
The MAX3874 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all SONET/
SDH specifications. The MAX3874A is the MAX3874
with a voltage-controlled oscillator (VCO) centered at
2.0212GHz.
The MAX3874 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm
✕
5mm 32-pin QFN with exposed pad package and oper-
ates over the -40°C to +85°C temperature range.
MAX3874
Ordering Information
PART
MAX3874EGJ
MAX3874AEGJ**
MAX3874AETJ+**
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
32 QFN
32 QFN
PKG
CODE
G3255-1
G3255-1
T3255-3
Applications
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
-40°C to +85°C 32 TQFN
**Contains
a VCO centered at 2.0212GHz.
+Denotes
lead-free package.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
C
FIL
0.068µF
V
CC
FILTER
OUT+
2.488Gbps DATA
SDI-
SLBI+
GND
+3.3V
V
CTRL
V
REF
2.488Gbps SYSTEM
LOOPBACK DATA
SIS
LREF
+3.3V
LOL
RATESET
GND
SLBI-
+3.3V
CAZ
0.1µF
+3.3V
FIL VCC_VCO CAZ-
SDI+
SDO+
SDO-
CML
+3.3V
CAZ+ FREFSET V
CC
MAX3745
OUT-
IN
MAX3874
SCLKO+
SCLKO-
CML
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
MAX3874
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +5.0V
Input Voltage Levels (SDI+, SDI-,
SLBI+, SLBI-) ..............................(V
CC
- 1.0V) to (V
CC
+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA
CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ...±22mA
Voltage at
LOL, LREF,
SIS, FIL, RATESET, FREFSET,
V
CTRL
, V
REF
, CAZ+, CAZ-......................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin QFN (derate 21.3mW/°C above +85°C) .........1384mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-55°C to +150°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Current
INPUT SPECIFICATION (SDI±, SLBI±)
Single-Ended Input Voltage
Range
Input Common-Mode Voltage
Input Termination to V
CC
Differential Input Voltage Range
(SDI±)
Threshold Adjustment Range
Threshold Control Voltage
Threshold Control Linearity
Threshold Setting Accuracy
Threshold Setting Stabiliity
Maximum Input Current
Reference Voltage Output
CML Differential Output
Impedance
CML Output Common-Mode
Voltage
I
CTRL
V
REF
Figure 2
15mV
≤
|V
TH
|
≤
80mV
80mV < |V
TH
|
≤
170mV
-18
-6
-12
-10
2.14
2.2
V
TH
V
CTRL
R
IN
V
IS
Figure 1
Figure 1
V
CC
-
0.8
V
CC
-
0.4
42.5
50
V
CC
+
0.4
V
CC
57.5
V
V
Ω
SYMBOL
I
CC
(Note 2)
CONDITIONS
MIN
TYP
175
MAX
215
UNITS
mA
THRESHOLD-SETTING SPECIFICATION (SDI±)
Threshold adjust enabled
Figure 2
Figure 2 (Note 3)
50
-170
0.3
±5
+18
+6
+12
+10
2.24
600
+170
2.1
mV
P-P
mV
V
%
mV
mV
µA
V
CML OUTPUT SPECIFICATION (SDO±, SCLKO±)
R
O
(Note 4)
85
100
V
CC
-
0.2
115
Ω
V
2
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
LVTTL Input High Voltage
LVTTL Input Low Voltage
LVTTL Input Current
LVTTL Output High Voltage
LVTTL Output Low Voltage
V
OH
V
OL
I
OH
= +20µA
I
OL
= -1mA
SYMBOL
V
IH
V
IL
-10
2.4
0.4
CONDITIONS
MIN
2.0
0.8
+10
TYP
MAX
UNITS
V
V
µA
V
V
LVTTL INPUT/OUTPUT SPECIFICATION (LOL,
LREF,
RATESET, FREFSET)
MAX3874
Note 1:
Note 2:
Note 3:
Note 4:
At -40°C, DC characteristics are guaranteed by design and characterization.
CML outputs open.
Voltage applied to V
CTRL
pin is from 0.3V to 2.1V when input threshold is adjusted from +170mV to -170mV.
R
L
= 50Ω to V
CC
.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 5)
PARAMETER
Serial Input Data Rate
Differential Input Voltage (SDI±)
Differential Input Voltage (SLBI±)
Jitter Transfer Bandwidth
Jitter Peaking
Sinusoidal Jitter Tolerance
(MAX3874)
Sinusoidal Jitter Tolerance
(MAX3874A)
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
(Note 8)
Jitter Generation
Differential Input Return Loss
(SDI±, SLBI±)
Output Edge Speed
CML Output Differential Swing
Clock-to-Q Delay
t
CLK-Q
J
GEN
-20log
| S
11
|
t
r
, t
f
J
BW
J
P
V
ID
SYMBOL
CONDITIONS
MAX3874 (RATESET = GND)
MAX3874 (RATESET = VCC)
MAX3874A
Threshold adjust disabled, Figure 1 (Note 6)
BER
≤
10
-10
MIN
TYP
2.488
2.667
2.0212
MAX
UNITS
Gbps
10
50
1.5
0.7
1600
800
2.0
0.1
mV
P-P
mV
P-P
MHz
dB
UI
P-P
MAX3874
MAX3874A
f
≤
J
BW
f = 100kHz
f = 1MHz
f = 10MHz
f = 1MHz (Note 7)
f = 10MHz (Note 7)
f = 100kHz
f = 1MHz
f = 10MHz
(Note 9)
100kHz to 2.5GHz
2.5GHz to 4GHz
20% to 80%
R
L
= 100Ω differential
(Note 10)
600
-40
3.1
0.62
0.44
8.0
0.93
0.65
>0.5
>0.3
7.1
0.82
0.54
2.7
16
15
110
800
1000
+40
4.0
mUI
RMS
dB
UI
P-P
UI
P-P
CML OUTPUT SPECIFICATION (SDO±, SCLKO±)
ps
mV
P-P
ps
_______________________________________________________________________________________
3
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
MAX3874
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL ACQUISITION/LOCK SPECIFICATION
Tolerated Consecutive Identical
Digits
Acquisition Time
LOL
Assert Time
Low-Frequency Cutoff for DC-
Offset Cancellation Loop
CLOCK HOLDOVER SPECIFICATION
Reference Clock Frequency
Maximum VCO Frequency Drift
(Note 12)
Table 4
400
ppm
BER
≤
10
-10
2000
1.0
2.3
4
10.0
Bits
ms
µs
kHz
Figure 4 (Note 11)
Figure 4
CAZ = 0.1µF
Note 5:
Minimum and maximum AC characteristics are guaranteed by design and characterization using the MAX3874.
Specifications apply to the MAX3874A only when noted.
Note 6:
Jitter tolerance is guaranteed (BER
≤
10
-10
) within this input voltage range. Input threshold adjust is disabled with V
CTRL
connected to V
CC
.
Note 7:
Measurements limited by equipment capability.
Note 8:
Measured using a 100mV
P-P
differential swing with a 20mVDC offset and an edge speed of 145ps (4th-order Bessel filter
with f
3dB
= 1.8GHz).
Note 9:
Measured with 10mV
P-P
differential input, 2
23
- 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz.
Note 10:
Relative to the falling edge of the SCLKO+ (Figure 3).
Note 11:
Measured at OC-48 data rate using a 0.068µF loop filter capacitor initialized to +3.6V.
Note 12:
Measured at OC-48 data rate under
LOL
condition with the CDR clock output set by the external reference clock.
Timing Diagrams
V
CC
+ 0.4V
800mV
V
CC
5mV
V
TH
(mV)
+188
+170
+152
THRESHOLD-SETTING STABILITY
(OVERTEMPERATURE AND POWER SUPPLY)
V
CC
- 0.4V
V
CC
(a) AC-COUPLED SINGLE-ENDED INPUT
5mV
0.3
1.1
1.3
V
CTRL
(V)
2.1
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
800mV
V
CC
- 0.4V
-152
-170
-188
V
CC
- 0.8V
(b) DC-COUPLED SINGLE-ENDED INPUT
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
4
_______________________________________________________________________________________
2.488Gbps/2.667Gbps Clock and
Data Recovery with Limiting Amplifier
Timing Diagrams (continued)
t
CLK
INPUT DATA
SCLKO+
t
CLK-Q
LOL ASSERT TIME
SDO
LOL OUTPUT
ACQUISITION TIME
DATA
DATA
MAX3874
Figure 3. Definition of Clock-to-Q Delay
Figure 4.
LOL
Assert Time and PLL Acquisition Time
Measurement
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED CLOCK AND DATA
(2.488Gbps, 2
23
- 1 PATTERN, V
IN
= 10mV
P-P
)
MAX3874toc01
RECOVERED CLOCK AND DATA
(2.67Gbps, 2
23
- 1 PATTERN, V
IN
= 10mV
P-P
)
MAX3874toc02
200mV/
div
200mV/
div
100ps/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)
MAX3874toc03
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
MAX3874toc04
JITTER TOLERANCE
(2.488Gbps, 2
23
- 1 PATTERN, V
IN
= 10mV
P-P
)
WITH ADDITIONAL 0.15UI
OF DETERMINISTIC JITTER
INPUT JITTER (UI
P-P
)
10
MAX3874 toc05
4.0
3.5
JITTER GENERATION (ps
RMS
)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
OC-48
PRBS = 2
23
- 1
100
1
BELLCORE
MASK
0.1
10ps/div
TOTAL WIDEBAND RMS JITTER = 1.60ps
PEAK-TO-PEAK JITTER = 12.20ps
0
5
10
15
20
25
30
10k
100k
1M
10M
WHITE-NOISE AMPLITUDE (mV
RMS
)
JITTER FREQUENCY (Hz)
_______________________________________________________________________________________
5
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