NTHS5441
Power MOSFET
−20 V, −5.3 A, P−Channel ChipFET]
Features
•
•
•
•
•
Low R
DS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature ChipFET Surface Mount Package
Pb−Free Package is Available
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V
(BR)DSS
−20 V
R
DS(on)
TYP
46 mW @ −4.5 V
S
I
D
MAX
−5.3 A
Applications
•
Power Management in Portable and Battery−Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
Rating
Drain−Source Voltage
Gate−Source Voltage
Continuous Drain Current
(T
J
= 150°C) (Note 1)
T
A
= 25°C
T
A
= 85°C
Pulsed Drain Current
Continuous Source Current
(Note 1)
Maximum Power Dissipation
(Note 1)
T
A
= 25°C
T
A
= 85°C
Operating Junction and Storage
Temperature Range
Symbol
V
DS
V
GS
I
D
−5.3
−3.8
I
DM
I
S
P
D
2.5
1.3
T
J
, T
stg
1.3
0.7
°C
−5.3
"20
−3.9
−3.9
−2.8
A
A
W
D
D
D
S
8
7
6
5
1
2
3
4
G
5 sec
Steady
State
−20
Unit
V
V
A
8
D
P−Channel MOSFET
"12
ChipFET
CASE 1206A
STYLE 1
1
PIN
CONNECTIONS
D
D
D
G
1
2
3
4
MARKING
DIAGRAM
8
A3
M
G
G
7
6
5
−55 to +150
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
A3 = Specific Device Code
M = Month Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NTHS5441T1
NTHS5441T1G
Package
ChipFET
ChipFET
(Pb−Free)
Shipping
†
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2005
1
July, 2005 − Rev. 13
Publication Order Number:
NTHS5441T1/D
NTHS5441
THERMAL CHARACTERISTICS
Characteristic
Maximum Junction−to−Ambient (Note 2)
t
v
5 sec
Steady State
Maximum Junction−to−Foot (Drain)
Steady State
Symbol
R
qJA
Typ
40
80
15
Max
50
95
20
°C/W
Unit
°C/W
R
qJF
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Static
Gate Threshold Voltage
Gate−Body Leakage
Zero Gate Voltage Drain Current
V
GS(th)
I
GSS
I
DSS
V
DS
= V
GS
, I
D
= −250
mA
V
DS
= 0 V, V
GS
=
"12
V
V
DS
= −16 V, V
GS
= 0 V
V
DS
= −16 V, V
GS
= 0 V,
T
J
= 85°C
On−State Drain Current (Note 3)
Drain−Source On−State Resistance (Note 3)
I
D(on)
r
DS(on)
V
DS
v
−5.0 V, V
GS
= −4.5 V
V
GS
= −3.6 V, I
D
= −3.7 A
V
GS
= −4.5 V, I
D
= −3.9 A
V
GS
= −2.5 V, I
D
= −3.1 A
Forward Transconductance (Note 3)
Diode Forward Voltage (Note 3)
Dynamic
(Note 4)
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Source−Drain Reverse Recovery Time
Q
G
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= −1.1 A, di/dt = 100 A/ms
V
DD
= −10 V, R
L
= 10
W
I
D
^
−1.0 A, V
GEN
= −4.5 V,
R
G
= 6
W
V
DS
= −5.0 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz
V
DS
= −10 V, V
GS
= −4.5 V,
I
D
= −3.9 A
9.7
1.2
3.6
710
400
140
14
22
42
35
30
30
55
100
70
60
ns
pF
22
nC
g
fs
V
SD
V
DS
= −10 V, I
D
= −3.9 A
I
S
= −2.1 A, V
GS
= 0 V
−20
−
−
0.050
0.046
0.070
12
−0.8
−1.2
0.06
−
0.083
mhos
V
−0.6
−1.2
"100
−1.0
−5.0
A
W
V
nA
mA
Symbol
Test Condition
Min
Typ
Max
Unit
2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
3. Pulse Test: Pulse Width
v
300
ms,
Duty Cycle
v
2%.
4. Guaranteed by design, not subject to production testing.
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2
NTHS5441
TYPICAL ELECTRICAL CHARACTERISTICS
20
−I
D,
DRAIN CURRENT (AMPS)
−5 V
−3.5 V
−3 V
T
J
= 25°C
−I
D,
DRAIN CURRENT (AMPS)
20
T
J
= −55°C
16
25°C
12
125°C
16
−4.5 V
−4 V
12
−2.5 V
8
−2 V
4
0
0
0.5
1
1.5
2
V
GS
= −1.5 V
8
4
0
2.5
3
0
0.5
1
1.5
2
2.5
3
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
0.2
I
D
= −3.9 A
T
J
= 25°C
0.15
0.2
Figure 2. Transfer Characteristics
T
J
= 25°C
0.15
V
GS
= 2.5 V
0.1
V
GS
= 3.6 V
0.05
V
GS
= 4.5 V
0.1
0.05
0
0
1
2
3
4
5
−V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
2
6
10
14
18
20
−I
D,
DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.6
R
DS(on),
DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
I
D
= −3.9 A
V
GS
= −4.5 V
1.4
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.2
1
0.8
0.6
−50
−25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
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3
NTHS5441
TYPICAL ELECTRICAL CHARACTERISTICS
−V
GS,
GATE−TO−SOURCE VOLTAGE (VOLTS)
1500
T
J
= 25°C
V
GS
= 0
5
11
Q
G
4
10
9
8
7
C, CAPACITANCE (pF)
1200
900
3
C
iss
C
oss
Q
GS
2
6
600
Q
GD
I
D
= −3.9 A
T
J
= 25°C
Q
GD
/Q
GS
= 3.0
0
1
2
3
4
5
6
7
8
9
5
4
3
2
1
0
10
300
0
0
1
C
rss
0
4
8
12
16
20
−V
DS
, DRAIN−TO−SOURCE VOLTAGE ()
Q
G
, TOTAL GATE CHARGE (nC)
Figure 6. Capacitance Variation
Figure 7. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
NORMALIZED EFFECTIVE TRANSIENT
THERMAL IMPEDANCE
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
0.0001
0.001
0.01
0.1
1
10
100
1000
t
2
DUTY CYCLE, D = t
1
/t
2
t
1
P
DM
PER UNIT BASE = R
qJA
= 80°C/W
T
JM
− T
A
= P
DM
Z
qJA
(t)
SURFACE MOUNTED
0.1
0.01
SQUARE WAVE PULSE DURATION (sec)
Figure 8. Normalized Thermal Transient Impedance, Junction−to−Ambient
5
−I
S
, SOURCE CURRENT (AMPS)
4
V
GS
= 0 V
T
J
= 25°C
3
2
1
0
0.1
0.3
0.5
0.7
0.9
−V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Diode Forward Voltage versus
Current
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4
−V
DS,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
NTHS5441
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
D
8
7
6
5
q
L
5
6
3
7
2
8
1
H
E
1
2
3
4
E
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
DIM
A
b
c
D
E
e
e1
L
H
E
q
MIN
1.00
0.25
0.10
2.95
1.55
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.014
0.011
0.071
0.075
5° NOM
MAX
0.043
0.014
0.008
0.122
0.067
e1
e
b
c
A
0.05 (0.002)
0.017
0.079
SOLDERING FOOTPRINT*
2.032
0.08
0.457
0.018
0.635
0.025
1.727
0.068
2.032
0.08
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
0.178
0.007
0.711
0.028
0.66
0.026
SCALE 20:1
mm
inches
Basic
Styles 1 and 4
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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