CY62177EV30 MoBL
®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
■
■
Functional Description
The CY62177EV30 is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL
®
) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or both
BHE and BLE are HIGH). The input and output pins (I/O
0
through
I/O
15
) are placed in a high impedance state when: deselected
(CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE
LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through
A
20
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written to the location specified on the
address pins (A
0
through A
20
). To read from the device, take
Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O
0
to I/O
7
. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O
8
to I/O
15
. See the
Truth Table on page 11
for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application
.
For a complete list of related resources,
click here.
Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M × 8 static RAM (SRAM)
Very high speed
❐
55 ns
Wide voltage range
❐
2.2 V to 3.7 V
Ultra low standby power
❐
Typical standby current: 3
A
❐
Maximum standby current: 25
A
Ultra low active power
❐
Typical active current: 4.5 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE Features
Automatic power down when deselected
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 48-pin TSOP I package and 48-ball FBGA
package
■
■
■
■
■
■
■
Logic Block Diagram
DATA IN
DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
2M × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BYTE
BHE
WE
OE
BLE
CE
2
CE
1
Power-Down
Circuit
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
BHE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document Number: 001-09880 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 17, 2015
CY62177EV30 MoBL
®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-09880 Rev. *N
Page 2 of 18
CY62177EV30 MoBL
®
Pin Configurations
Figure 1. 48-pin TSOP I pinout (Front View)
[1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Figure 2. 48-ball FBGA pinout (Top View)
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
3
A
0
A
3
A
5
A
17
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
Vcc
Vss
I/O
6
I/O
7
A
20
A
B
C
D
E
F
G
H
I/O
12
NC
I/O
13
A
19
A
8
A
14
A
12
A
9
Product Portfolio
Power Dissipation
Product
Min
CY62177EV30LL
2.2
V
CC
Range (V)
Typ
[3]
3.0
Max
3.7
55
Speed
(ns)
Operating I
CC
(mA)
f = 1 MHz
Typ
[3]
4.5
Max
5.5
35
f = f
Max
Typ
[3]
Max
45
Standby I
SB2
(A)
Typ
[3]
3
Max
25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-pin TSOP I package has to be tied to V
CC
to use the device as a 2 M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4 M × 8 SRAM by tying the BYTE signal to V
SS
. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O
8
to I/O
14
pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 001-09880 Rev. *N
Page 3 of 18
CY62177EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential
[4, 5]
............... –0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in High Z state
[4, 5]
...................... –0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[4, 5]
................... –0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Device
CY62177EV30LL
Range
Ambient
Temperature
V
CC
[6]
Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
V
CC
operating supply current
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
V
CC
= 2.20 V
V
CC
= 2.70 V
V
CC
= 2.20 V
V
CC
= 2.70 V
55 ns
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
–
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
Typ
[7]
–
–
–
–
–
–
–
–
–
–
35
4.5
3
Max
–
–
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.7
[8]
+1
+1
45
5.5
25
Unit
V
V
V
V
V
V
V
V
A
A
mA
mA
A
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.7 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.7 V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
Max
= 1/t
RC
f = 1 MHz
I
SB2 [9, 10]
Automatic CE power down
current – CMOS inputs
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V or
(BHE and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V, f = 0,
V
CC
= 3.7 V
Notes
4. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100
s
ramp time from 0 to V
CC
(min) and 200
s
wait time after V
CC
stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
8. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE pin in the 48-pin TSOP I package has to be tied to V
CC
to use the device as a 2 M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4 M × 8 SRAM by tying the BYTE signal to V
SS
. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O
8
to I/O
14
pins are not used.
10. Chip enables (CE
1
and CE
2
), BYTE, and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document Number: 001-09880 Rev. *N
Page 4 of 18
CY62177EV30 MoBL
®
Capacitance
Parameter
[11]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
15
15
Unit
pF
pF
Thermal Resistance
Parameter
[11]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
FBGA
38.10
7.54
TSOP I
55.91
9.39
Unit
C/W
C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
V
CC
90%
90%
10%
10%
GND
Fall Time = 1 V/ns
R2
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
R
TH
V
Parameter
R1
R2
R
TH
V
TH
2.5 V
16667
15385
8000
1.20
3.3 V
1103
1554
645
1.75
Unit
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-09880 Rev. *N
Page 5 of 18
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