PD -
97115D
IRFB4310ZPbF
IRFS4310ZPbF
IRFSL4310ZPbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
G
S
D
V
DSS
R
DS(on)
typ.
max.
I
D
(Silicon Limited)
I
D
(Package Limited)
D
D
100V
4.8m
:
6.0m
:
127A
c
120A
G
D
S
G
D
S
G
D
S
TO-220AB
IRFB4310ZPbF
G
D
2
Pak
IRFS4310ZPbF
D
TO-262
IRFSL4310ZPbF
S
G ate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
f
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
127c
90c
120
560
250
1.7
± 20
18
-55 to + 175
300
10lbxin (1.1Nxm)
475
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
e
Avalanche Current
c
Repetitive Avalanche Energy
g
mJ
A
mJ
Thermal Resistance
Symbol
R
JC
R
CS
R
JA
R
JA
Parameter
Junction-to-Case
k
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
k
Junction-to-Ambient (PCB Mount) , D Pak
jk
2
Typ.
–––
0.50
–––
–––
Max.
0.6
–––
62
40
Units
°C/W
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1
4/23/12
IRFB/S/SL4310ZPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G
Parameter
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.11
4.8
–––
–––
–––
–––
–––
0.7
–––
–––
6.0
4.0
20
250
100
-100
–––
nA
V
Conditions
V
GS
= 0V, I
D
= 250μA
V
(BR)DSS
/T
J
Breakdown Voltage Temp. Coefficient
V/°C Reference to 25°C, I
D
= 5mAd
m V
GS
= 10V, I
D
= 75A
g
V
μA
V
DS
= V
GS
, I
D
= 150μA
V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
V
GS
= -20V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
150
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
120
29
35
85
20
60
55
57
6860
490
220
570
920
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
pF
ns
–––
170
–––
S
nC
I
D
= 75A
V
DS
=50V
V
GS
= 10V
g
Conditions
V
DS
= 50V, I
D
= 75A
I
D
= 75A, V
DS
=0V, V
GS
= 10V
V
DD
= 65V
I
D
= 75A
R
G
= 2.7
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz, See Fig. 5
V
GS
= 0V, V
DS
= 0V to 80V
i,
See Fig. 11
V
GS
= 0V, V
DS
= 0V to 80V
h
C
oss
eff. (ER) Effective Output Capacitance (Energy Related) –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)h –––
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
d
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
–––
–––
–––
–––
––– 127c
–––
–––
40
49
58
89
2.5
–––
A
nC
560
1.3
A
A
V
ns
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
g
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 85V,
I
F
= 75A
di/dt = 100A/μs
g
G
S
D
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width
400μs; duty cycle
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
is measured at T
J
approximately 90°C
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.28mH
R
G
= 25, I
AS
= 58A, V
GS
=10V. Part not recommended for use
above the Eas value and test conditions.
I
SD
75A, di/dt
600A/μs, V
DD
V
(BR)DSS
, T
J
175°C.
2
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IRFB/S/SL4310ZPbF
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
100
10
4.5V
4.5V
60μs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
60μs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
2.5
Fig 2.
Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
ID = 75A
2.0
ID, Drain-to-Source Current
)
VGS = 10V
100
TJ = 175°C
10
(Normalized)
1.5
TJ = 25°C
1
1.0
VDS = 50V
0.1
2.0
3.0
4.0
5.0
60μs PULSE WIDTH
6.0
7.0
8.0
0.5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
12000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A
VDS = 80V
VDS= 50V
VDS= 20V
10000
16
C, Capacitance (pF)
8000
Ciss
12
6000
8
4000
2000
Coss
Crss
4
0
1
10
100
0
0
40
80
120
160
200
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL4310ZPbF
1000
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
100
TJ = 175°C
1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
1msec
100μsec
10
TJ = 25°C
10
10msec
1
1
VGS = 0V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
DC
10
100
0.1
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
Fig 8.
Maximum Safe Operating Area
130
140
LIMITED BY PACKAGE
120
ID, Drain Current (A)
ID = 5mA
120
100
80
60
40
20
0
25
50
75
100
125
150
175
TC, Case Temperature (°C)
110
100
90
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
3.0
Fig 10.
Drain-to-Source Breakdown Voltage
2000
EAS, Single Pulse Avalanche Energy (mJ)
2.5
1600
ID
TOP
18A
29A
BOTTOM
58A
2.0
Energy (μJ)
1200
1.5
800
1.0
0.5
400
0.0
0
20
40
60
80
100
0
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB/S/SL4310ZPbF
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20
0.10
0.05
0.02
J
J
1
R
1
R
1
2
R
2
R
2
R
3
R
3
3
R
4
R
4
C
1
2
3
4
4
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Ci=
iRi
Ci iRi
Ri (°C/W)
0.018756
0.159425
0.320725
0.101282
(sec)
0.000007
0.000117
0.001817
0.011735
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
0.001
1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
0.01
0.05
Avalanche Current (A)
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tj
= 150°C and
Tstart =25°C (Single Pulse)
0.10
Duty Cycle = Single Pulse
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
500
EAR , Avalanche Energy (mJ)
400
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 58A
300
200
100
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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