74VHC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 165 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC273MTR
74VHC273TTR
DESCRIPTION
The 74VHC273 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/14
74VHC273
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
75
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
Value
2 to 5.5
0 to 5.5
0 to V
CC
-55 to 125
0 to 100
0 to 20
Unit
V
V
V
°C
ns/V
1) V
IN
from 30% to 70% of V
CC
3/14
74VHC273
Table 7: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PHL
Propagation Delay
Time
CLEAR to Q
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
W
t
W
CLEAR Pulse
Width LOW
CLOCK Pulse
Width HIGH or
LOW
Setup Time D to
CLOCK, HIGH or
LOW
Hold Time D to
CLOCK, HIGH or
LOW
Removal Time
CLEAR to CLOCK
Maximum Clock
Frequency
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
3.3
(*)
5.0
(**)
15
50
15
50
50
50
75
50
120
80
120
75
165
110
1.5
1.0
C
L
(pF)
15
50
15
50
15
50
15
50
T
A
= 25°C
Min.
Typ.
8.7
11.2
5.8
7.3
8.9
11.4
5.2
6.7
Max.
13.6
17.1
9.0
11.0
13.6
17.1
8.5
10.5
5.0
5.0
5.5
5.0
5.5
4.5
1.0
1.0
2.5
2.0
65
45
100
70
1.5
1.0
Value
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
16.0
19.5
10.5
12.5
16.0
19.5
10.0
12.0
6.0
5.0
6.5
5.0
6.5
4.5
1.0
1.0
2.5
2.0
65
45
100
70
1.5
1.0
ns
MHz
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
16.0
19.5
10.5
12.5
16.0
19.5
10.0
12.0
6.0
5.0
6.5
5.0
6.5
4.5
1.0
1.0
2.5
2.0
ns
ns
ns
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
CLOCK to Q
t
s
t
h
t
REM
f
MAX
ns
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
Note 1: Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Table 8: Capacitive Characteristics
Test Condition
Symbol
Parameter
T
A
= 25°C
Min.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
Typ.
7
31
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per
Flip-Flop)
5/14
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