74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
Rev. 5 — 29 November 2012
Product data sheet
1. General description
The 74LVC109A is a dual positive edge triggered JK flip-flop featuring:
•
•
•
•
individual J and K inputs
clock (CP) inputs
set (SD) and reset (RD) inputs
complementary Q and Q outputs
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode
select function table. The J and K inputs must be stable one set-up time before the
LOW-to-HIGH clock transition for predictable operation. The JK design allows operation
as a D-type flip-flop by tying the J and K inputs together.
Schmitt trigger action in the clock input makes the circuit highly tolerant of slower clock
rise and fall times.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
All types are specified from
40
C to +125
C.
Type number
74LVC109D
74LVC109DB
74LVC109PW
Package
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
4. Functional diagram
5 11
1SD 2SD
2
14
4
12
3
13
SD
1Q
1J
Q
J
2J
2Q
1CP
CP
2CP
FF
1Q
1K
Q
K
2Q
2K
RD
1RD 2RD
1 15
mna858
6
10
5
2
4
S
1J
C1
7
1K
R
(a)
6
11
14
12
13
15
S
1J
C1
9
1K
R
(b)
mna856
10
7
9
3
1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Q
C
K
Q
J
C
C
C
C
C
C
C
S
mna859
R
CP
C
C
Fig 3.
Logic diagram for one flip-flop
74LVC109
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 29 November 2012
2 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
1RD
1J
1K
1CP
1SD
1Q
1Q
GND
1
2
3
4
16 V
CC
15 2RD
14 2J
13 2K
109
5
6
7
8
001aad064
12 2CP
11 2SD
10 2Q
9
2Q
Fig 4.
Pin configuration SO16 and (T)SSOP16
5.2 Pin description
Table 2.
Symbol
1RD
1J
1K
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2K
2J
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set input (active LOW)
clock input (LOW-to-HIGH; edge-triggered)
synchronous input
synchronous input
asynchronous reset input (active LOW)
supply voltage
74LVC109
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 29 November 2012
3 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Function selection
[1]
Input
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
Operating modes
Output
nRD
H
L
L
H
H
H
H
nCP
X
X
X
nJ
X
X
X
h
l
h
l
nK
X
X
X
l
l
h
h
nQ
H
L
H
q
L
H
q
nQ
L
H
H
q
H
L
q
L
H
L
H
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
50
100
-
500
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74LVC109
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 29 November 2012
4 of 17
NXP Semiconductors
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
1.7
2.0
-
-
-
-
40 C
to +85
C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
40 C
to +125
C
Min
1.08
1.7
2.0
-
-
-
-
-
-
0.12
0.7
0.8
0.65
V
CC
-
Max
V
V
V
V
V
V
V
Unit
0.65
V
CC
-
0.35
V
CC
-
0.35
V
CC
V
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND -
current
74LVC109
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 29 November 2012
5 of 17
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
