NB7L86M
2.5V/3.3V 12 Gb/s Differential
Clock/Data SmartGate with
CML Output and Internal
Termination
The NB7L86M is a multi−function differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The NB7L86M is an
ultra−low jitter multi−logic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.
Differential inputs incorporate internal 50
W
termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50
W
termination, and 400 mV
output swing when externally terminated 50
W
to V
CC
.
The device is housed in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
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MARKING
DIAGRAM*
16
1
1
QFN16
MN SUFFIX
CASE 485G
NB7L
86M
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Maximum Input Clock Frequency up to 8 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
*For additional marking information, refer to
Application Note AND8002/D.
30 ps Typical Rise and Fall Times
90 ps Typical Propagation Delay
2 ps Typical Within Device Skew
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV Peak−to−Peak Output) Differential Output
50
W
Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
•
These are Pb−Free Devices
VTD0
D0
D0
VTD0
50
W
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Q
50
W
50
W
Q
VTD1
D1
D1
VTD1
50
W
50
W
SEL
50
W
VTSEL
SEL
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2012
March, 2012
−
Rev. 7
1
Publication Order Number:
NB7L86M/D
NB7L86M
VTD0 D0
16
V
CC
SEL
SEL
VTSEL
1
2
NB7L86M
3
4
5
6
7
8
10
9
Q
V
CC
15
D0 VTD0 Exposed Pad (EP)
14
13
12
11
V
EE
Q
VTD1 D1
D1 VTD1
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1, 9
2
3
4
5
6
7
8
10
11
12
13
14
15
16
−
Name
V
CC
SEL
SEL
V
TSEL
V
TD1
D1
D1
V
TD1
Q
Q
V
EE
V
TD0
D0
D0
V
TD0
EP
I/O
Power Supply
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
−
−
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
−
CML Output
CML Output
Power Supply
−
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
−
−
Description
Positive supply voltage. All V
CC
pins must be externally connected to power
supply to guarantee proper operation.
Inverted differential select logic input.
Non−inverted differential select logic Input.
Common internal 50
W
termination pin for SEL/SEL. See Table 6. (Note 1)
Internal 50
W
termination pin for D1. See Table 6. (Note 1)
Non−inverted differential clock/data input D1. (Note 1)
Inverted differential clock/data input D1. (Note 1)
Internal 50
W
termination pin for D1. See Table 6. (Note 1)
Non−inverted output with internal 50
W
source termination resistor. (Note 2)
Inverted output with internal 50
W
source termination resistor. (Note 2)
Negative supply voltage. All V
EE
pins must be externally connected to power
supply to guarantee proper operation.
Internal 50
W
termination pin for D0. (Note 1)
Non−inverted differential clock/data input D0. (Note 1)
Non−inverted differential clock/data input D0. (Note 1)
Internal 50
W
termination pin for D0. (Note 1)
Exposed Pad. Thermal pad on the package bottom must be attached to a
heatsinking conduit to improve heat transfer. It is recommended to connect the EP
to the lower potential (V
EE
).
1. In the differential configuration when the input termination pins (V
TDx
, V
TDx
, V
TSEL
) are connected to a common termination voltage or left
open, and if no signal is applied on Dx, Dx, SEL and SEL then the device will be susceptible to self−oscillation.
2. CML output require 50
W
receiver termination resistor to VCC for proper operation.
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2
NB7L86M
VTD0
VT or
V
BB
V
CC
VTD0
VTD1
50
W
D0
D0
50
W
50
W
Q
Q
D1
D1
50
W
50
W
50
W
V
EE
V
CC
SEL
D0
0
0
0
0
Table 2. AND/NAND TRUTH TABLE
(Note 3)
∝
D1
0
0
1
1
b
SEL
0
1
0
1
∝
AND b
Q
0
0
0
1
m
VTD1
R
D
3. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
VTSEL
SEL
b
Figure 3. Configuration for AND/NAND Function
50
W
D0
D0
50
W
50
W
D1
D1
50
W
50
W
50
W
Q
Q
VTD0
m
VTD0
Table 3. OR/NOR TRUTH TABLE
(Note 4)
m
D0
0
0
1
1
D1
1
1
1
1
b
SEL
0
1
0
1
m
or
b
Q
0
1
1
1
VTD1
V
CC
VT or V
BB
VTD1
4. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
VTSEL
SEL
b
SEL
Figure 4. Configuration for OR/NOR Function
VTD0
50
W
D0
D0
50
W
50
W
D1
D1
Q
Q
m
VTD0
Table 4. XOR/XNOR TRUTH TABLE
(Note 5)
m
D0
0
0
1
50
W
1
D1
1
1
0
0
b
SEL
0
1
0
1
m
XOR
b
Q
0
1
1
0
VTD1
VTD1
50
W
50
W
VTSEL
SEL
5. D0, D1, SEL are complementary of D0, D1, SEL unless
specified otherwise.
SEL
b
Figure 5. Configuration for XOR/XNOR Function
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3
NB7L86M
VTD0
D0
D0
VTD0
50
W
50
W
Q
Q
50
W
Table 5. 2:1 MUX TRUTH TABLE
(Note 6)
SEL
1
0
Q
D1
D0
VTD1
D1
D1
VTD1
6. D0, D1, SEL are complementary of D0, D1, SEL
unless specified otherwise.
50
W
50
W
50
W
SEL
VTSEL
SEL
Figure 6. Configuration for 2:1 MUX Function
Table 6. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
7. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
Value
> 1500 V
> 50 V
> 500 V
Pb−Free Pkg
Level 1
Moisture Sensitivity (Note 7)
UL 94 V−0 @ 0.125 in
400
Table 7. MAXIMUM RATINGS
Symbol
V
CC
V
I
V
INPP
I
IN
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input Voltage
Differential Input Voltage |D
−
D|
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 8)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 8)
QFN−16
QFN−16
QFN−16
Condition 1
V
EE
= 0 V
V
EE
= 0 V
V
CC
−
V
EE
≥
V
CC
−
V
EE
<
Continuous
Surge
Continuous
Surge
QFN−16
2.8 V
2.8 V
V
EE
≤
V
I
≤
V
CC
Condition 2
Rating
3.6
3.6
2.8
|V
CC
−
V
EE
|
25
50
25
50
−40
to +85
−65
to +150
42
36
3 to 4
265
265
Units
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
8. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
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NB7L86M
Table 8. DC CHARACTERISTICS
(
V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V, T
A
=
−40°C
to +85°C)
Symbol
I
CC
V
OH
V
OL
V
th
V
IH
V
IL
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
R
TIN
R
TOUT
R
Temp Coef
Characteristic
Power Supply Current (Inputs and Outputs Open)
Output HIGH Voltage (Notes 9 and 10)
Output LOW Voltage (Notes 9 and 10)
Input Threshold Reference Voltage Range (Note 11)
Single−ended Input HIGH Voltage (Note 12)
Single−ended Input LOW Voltage (Note 12)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
Input LOW Current
Internal Input Termination Resistor
Internal Output Termination Resistor
Internal I/O Termination Resistor Temperature Coefficient
D0/D0/D1/D1
SEL/SEL
D0/D0/D1/D1
SEL/SEL
V
CC
−
60
V
CC
−
460
1125
V
th
+ 75
V
EE
1200
V
EE
1163
75
0
0
−50
−50
45
45
50
20
50
20
50
50
6.38
Min
Typ
38
V
CC
−
30
V
CC
−
400
Max
50
V
CC
V
CC
−
310
V
CC
−
75
V
CC
V
CC
−
150
V
CC
V
CC
−
75
V
CC
– 38
2500
150
150
100
100
55
55
Unit
mA
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
W
W
mW/°C
Differential Input Driven Single−Ended (see Figures 16 & 18)
Differential Inputs Driven Differentially (see Figures 17 & 19)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range.
Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually
under normal operating conditions and not valid simultaneously.
9. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation.
10. Input and output parameters vary 1:1 with V
CC
.
11. V
th
is applied to the complementary input when operating in single−ended mode.
12. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
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