Ordering number : :ENA1028D
Ordering number ENA1951
LC87F2G08A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F2G08A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as
8K-byte flash ROM, 256-byte RAM, an On-chip-debugger, a 16-bit timers/counters, two 8-bit timers, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an
asynchronous/synchronous SIO interface, a UART interface, a 12-bit/8-bit 8-channel AD converter, a system clock
frequency divider, an internal reset and an interrupt feature.
Features
Flash
ROM
•
8192
×
8 bits
•
Capable of On-board programming with
wide range (2.2 to 5.5V) of voltage source.
•
Block-erasable in 128 byte units
•
Writable in 2-byte units
RAM
•
256
×
9 bits
Package
Form
•
MFP24SJ (300mil): Lead-/Halogen-free type
•
SSOP24 (225mil): Lead-free type
•
VCT24 (3.5×3.5): Lead-/Halogen-free type (build-to-order)
•
MFP24S (300mil): Lead-free type (discontinued)
Package Dimensions
unit : mm (typ)
3419
13.0
24
6.0
8.0
1 2
(1.0)
1.0
0.4
1.9 MAX
0.15
SANYO : MFP24SJ(300mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.4
D0512HK/O0312HKIM 20120913-S00008 No.A1028-1/29
0.1 (1.5)
0.45
LC87F2G08A
Package Dimensions
unit : mm (typ)
3287
6.5
24
13
Package Dimensions
unit : mm (typ)
3322A
TOP VIEW
3.5
(C0.17)
SIDE VIEW
(Build-to-order)
BOTTOM VIEW
(0.13)
(0.125)
4.4
6.4
3.5
0.5
0.4
1
0.5
(0.5)
0.22
12
24
2 1
0.15
0.5
SIDE VIEW
0.8
(0.5)
1.5max
0.25
(1.3)
(0.035)
SANYO : VCT24(3.5X3.5)
SANYO : SSOP24(225mil)
Package Dimensions
unit : mm (typ)
3112B
12.5
24
13
0.1
(Discontinued)
5.4
7.6
1
1.0
(0.75)
0.35
12
0.15
SANYO : MFP24S(300mil)
Minimum
Bus Cycle
•
83.3ns (12MHz at VDD=2.7V to 5.5V)
•
100ns (10MHz at VDD=2.2V to 5.5V)
•
250ns (4MHz at VDD=1.8V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
Minimum
Instruction Cycle Time
•
250ns (12MHz at VDD=2.7V to 5.5V)
•
300ns (10MHz at VDD=2.2V to 5.5V)
•
750ns (4MHz at VDD=1.8V to 5.5V)
0.1
(1.5)
1.7max
0.63
No.A1028-2/29
LC87F2G08A
Ports
•
Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
Ports I/O direction can be designated in 4-bit units
•
Dedicated oscillator ports/input ports
•
Reset pin
•
Power pins
11 (P1n, P20, P21, P70)
8 (P0n)
2 (CF1/XT1, CF2/XT2)
1 (RES)
2 (VSS1, VDD1)
Timers
•
Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
High-Speed
Clock Counter
•
Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
•
Can generate output real time.
SIO
•
SIO0: 8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
•
Full Duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2 bits in continuous data transmission)
•
Built-in baudrate generator
AD
Converter: 12 bits/8 bits
×
8 channels
•
12 bits/8 bits AD converter resolution selectable
Remote
Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
No.A1028-3/29
LC87F2G08A
Clock
Output Function
•
Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
•
Can generate the source clock for the subclock
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Interrupts
•
18 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/base timer
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
Port 0
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
Oscillation
Circuits
•
Internal oscillation circuits
Low-speed RC oscillation circuit :
For system clock (100kHz)
Medium-speed RC oscillation circuit : For system clock (1MHz)
Multifrequency RC oscillation circuit : For system clock (8MHz)
•
External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock, with internal Rf
Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the
CF oscillation circuit resumes operation.
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
No.A1028-4/29
LC87F2G08A
Internal
Reset Function
•
Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
•
Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
Onchip
Debugger
•
Supports software debugging with the IC mounted on the target board.
•
Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)
Data
Security Function (flash versions only)
•
Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Development
Tools
•
On-chip debugger: (1) TCB87 type B + LC87D2G08A
(2) TCB87 TypeB + LC87F2G08A
(3) TCB87 TypeC (3 wire version) + LC87D2G08A
(4) TCB87 TypeC (3 wire version) + LC87F2G08A
Note: LC87F2G08A has an On-chip debugger but its function is limited.
No.A1028-5/29
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