CY23S05SXI-1: 产品描述Phase Locked Loops - PLL Zero Delay Buffer IND; 产品类别热门应用无线/射频/通信; 文件大小271KB，共13页; 制造商Cypress(赛普拉斯)

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CY23S05SXI-1概述

Phase Locked Loops - PLL Zero Delay Buffer IND

CY23S05SXI-1规格参数

参数名称	属性值
产品种类 Product Category	Phase Locked Loops - PLL
制造商 Manufacturer	Cypress(赛普拉斯)
RoHS	Details
系列 Packaging	Tube
Moisture Sensitive	Yes
工厂包装数量 Factory Pack Quantity	194

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CY23S09, CY23S05

Low Cost 3.3 V Spread Aware

Zero Delay Buffer

Features

■

10 MHz to 100 MHz and 133 MHz operating range, compatible

with CPU and PCI bus frequencies

Zero input-output propagation delay

Multiple low skew outputs

❐

Output-output skew less than 250 ps

❐

Device-device skew less than 700 ps

❐

One input drives five outputs (CY23S05)

❐

One input drives nine outputs, grouped as 4 + 4 + 1

(CY23S09)

Less than 200 ps Cycle-to-cycle jitter

Test mode to bypass PLL (CY23S09 only, see

Select Input

Decoding for CY23S09

on page 4)

Available in space saving 16-pin, 150-mil SOIC, 4.4 mm

TSSOP (CY23S09) or 8-pin, 150-mil

SOIC package (CY23S05)

3.3 V operation, advanced 0.65 CMOS technology

Spread Aware

All parts have on-chip PLLs that lock to an input clock on the REF

pin. The PLL feedback is on-chip and is obtained from the

CLKOUT pad.

The CY23S09 has two bans of four outputs each, which can be

controlled by the select inputs as shown in the Select Input

Decoding table on

Select Input Decoding for CY23S09

on page

4. If all output clocks are not required, Bank B can be

three-stated. The select inputs also allow the input clock to be

directly applied to the outputs for chip and system testing

purposes.

The CY23S09 and CY23S05 PLLs enter a power down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0

A

of current draw (for commercial temperature

devices) and 25.0

A

(for industrial temperature devices). The

CY23S09 PLL shuts down in one additional case, as shown in

the

Select Input Decoding for CY23S09

on page 4.

Multiple CY23S09 and CY23S05 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

All outputs have less than 200 ps of cycle-to-cycle jitter. The input

to output propagation delay on both devices is guaranteed to be

less than 350 ps; the output to output skew is guaranteed to be

less than 250 ps.

The CY23S05 and CY23S09 is available in two different config-

urations, as shown in the

Ordering Information

on page 8. The

CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H

and CY23S09-1H is the high drive version of the -1, and its rise

and fall times are much faster than -1.

For a complete list of related resources, click

here.

■

Functional Description

The CY23S09 is a low cost 3.3 V zero delay buffer designed to

distribute high speed clocks and is available in a 16-pin SOIC

package. The CY23S05 is an 8-pin version of the CY23S09. It

accepts one reference input, and drives out five low skew clocks.

The -1H versions of each device operate at up to 100 and

133 MHz frequencies and have higher drive than the -1 devices.

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 38-07296 Rev. *I

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 07, 2014

CY23S05SXI-1相似产品对比

	CY23S05SXI-1	CY23S05SI-1	FP70P-2290-BB50W	CY23S05SXC-1T
描述	Phase Locked Loops - PLL Zero Delay Buffer IND	Phase Locked Loops - PLL Zero Delay Buffr IND	Fixed Resistor, Metal Film, 2W, 229ohm, 500V, 0.1% +/-Tol, 50ppm/Cel,	Phase Locked Loops - PLL Clock Distribution
产品种类 Product Category	Phase Locked Loops - PLL	Phase Locked Loops - PLL	-	Phase Locked Loops - PLL
制造商 Manufacturer	Cypress(赛普拉斯)	Cypress(赛普拉斯)	-	Cypress(赛普拉斯)

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