Ordering number : ENA1007
LC87F6D64A
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
8-bit 1-chip Microcontroller
Overview
The LC87F6D64A is 8-bit microcomputer with the following on-chip functional blocks:
•
CPU: operable at a minimum bus cycle time of 100ns
•
64K-byte flash ROM (re-writeable on board/On-chip debugger)
•
On-chip RAM: 2048 byte
•
VFD automatic display controller/driver
•
16-bit timer/counter (can be divided into two 8-bit timers)
•
two 8-bit timer with prescaler
•
timer for use as date/time clock
•
Day-Minute-Second Counter (DMSC)
•
System clock divider function
•
Synchronous serial I/O port (with automatic block transmit /receive function)
•
Asynchronous/synchronous serial I/O port
•
Remote control receive function
•
8-channel×8-bit AD converter
•
14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
http://onsemi.com
Features
Flash
ROM
•
Single 5V power supply, writeable on-board.
•
Block erase in 128 byte units
•
65536
×
8 bits
RAM
•
2048
×
9 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.21
30508HKIM 20071127-S00004 No.A1007-1/19
LC87F6D64A
Minimum
Bus Cycle Time
•
100ns (10MHz) VDD=3.0 to 5.5V
•
150ns (4MHz) VDD=2.5 to 5.5V
Note: The bus cycle time indicates ROM read time.
Minimum
Instruction Cycle Time (tCYC)
•
300ns (10MHz) VDD=3.0 to 5.5V
•
750ns (4MHz) VDD=2.5 to 5.5V
Ports
•
Input/output ports
Data direction programmable for each bit individually: 10 (P1n, P7n)
Data direction programmable in nibble units:
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
•
VFD output ports
Large current outputs for digits:
9 (S0/T0 to S8/T8)
Large current outputs for digits/segments:
7 (S9/T9 to S15/T15)
Digit/segment outputs:
8 (S16 to S23)
Segment outputs:
30 (S24 to S53)
•
Oscillator pins:
2 (CF1/XT1, CF2/XT2)
•
Reset pin:
1 (RES)
•
Power supply:
4 (VSS1, VDD1 to VDD3)
•
VFD power supply:
1 (VP)
VFD
Automatic Display Controller
•
Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output
(pins 9 to 23 can be used for output of digit waveforms).
parallel-drive available for large current VFD.
•
16-step dimmer function available
Timers
•
Timer 0: 16-bit timer/counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register
+ 8-bit counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
•
Timer 4: 8-bit timer with 6-bit prescaler
•
Timer 5: 8-bit timer with 6-bit prescaler
•
Base Timer
1) The clock signal can be selected from any of the following.
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
•
Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
SIO
•
SIO 0: 8-bit synchronous serial interface
1) LSB first /MSB first function available
2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3) Consecutive automatic data communication
(1 to 256 bits (communication available for each bit) (stop and reopening available for each byte))
•
SIO 1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
No.A1007-2/19
LC87F6D64A
AD
Converter: 8 bits
×
8 channels
Remote
Control Receiver Circuit (sharing pins with P70/INT0/RMIN)
•
Noise rejection function
(Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
•
Supporting reception formats with a guide-pulse of half-clock/clock/none.
•
Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
•
X’tal HOLD mode release function
Watchdog
Timer
•
The watching timer period is set using an external RC.
•
Watchdog timer can produce interrupt, system reset.
Clock
Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts:
14 sources, 10 vector interrupts
•
Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is refused.
•
If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
SIO0
SIO1
ADC
Port0/T4/T5
INT0
INT1
INT2/T0L/remote control receiver
INT3/Base timer 0/1
T0H
Interrupt Signal
•
Priority Level: X>H>L
•
For equal priority levels, vector with lowest address takes precedence.
Subroutine
Stack Levels: 1024 levels maximum (Stack is located in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
Oscillation
Circuits
•
On-chip RC oscillation circuit for system clock use.
•
On-chip CF oscillation circuit* for system clock use. (Rf built in)
•
On-chip Crystal oscillation circuit* low speed system clock use. (Rf built in)
•
Frequency variable RC oscillation circuit (internal) for system clock.
1) Adjustable in
±4%
(typ) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
* The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of
commonness.
No.A1007-3/19
LC87F6D64A
System
Clock Divider Function
•
Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs.
(Using 10MHz main clock)
Standby
Function
•
HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate
but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
•
HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped.
1) The CF, RC, X’tal and frequency variable RC oscillators automatically stop operation.
2) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) a specified level is input to at least one of INT0, INT1, INT2
(3) an interrupt condition arises at port 0
•
X’tal HOLD mode.
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base-timer are stopped.
1) The CF, RC, frequency variable RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) Setting at least one of the INT0, INT1 and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
On-chip
Debugger
•
Supports software debugging with the IC mounted on the target board.
Package
Form
•
QFP80(14×14): Lead-free type
Development
Tools
•
On-chip debugger: TCB87- type-B + LC87F6D64A
No.A1007-4/19
LC87F6D64A
Package Dimensions
unit : mm (typ)
3255
17.2
60
61
41
40
80
1
(0.83)
0.65
0.25
20
21
0.15
3.0max
0.1
(2.7)
SANYO : QFP80(14X14)
Pin Assignment
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S38
S39
VDD3
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
P10/SO0
P11/SI0/SB0
P12/SCK0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
14.0
17.2
0.8
14.0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/INT2/T0IN
P17/INT3/T0IN
RES
VSS1
CF1/XT1
CF2/XT2
VDD1
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P70/INT0/T0LCP/RMIN
P71 INT1/T0HCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
LC87F6D64A
S17
S16
VDD2
VP1
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
Top view
QFP80(14×14) “Lead-free Type”
No.A1007-5/19
模拟电子
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