19-3544; Rev 0; 2/05
KIT
ATION
EVALU
E
BL
AVAILA
Dual, 65Msps, 14-Bit, IF/Baseband ADC
General Description
The MAX12557 is a dual 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12557 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 610mW while delivering a typical 72.5dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12557 features a 166µW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12557 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12557
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12557 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12557 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12557 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12527 data sheet.
Features
♦
Direct IF Sampling Up to 400MHz
♦
Excellent Dynamic Performance
74.1dB/72.5dB SNR at f
IN
= 70MHz/175MHz
83.4dBc/79.5dBc SFDR at f
IN
= 70MHz/175MHz
♦
3.3V Low-Power Operation
637mW (Differential Clock Mode)
610mW (Single-Ended Clock Mode)
♦
Fully Differential or Single-Ended Analog Input
♦
Adjustable Differential Analog Input Voltage
♦
750MHz Input Bandwidth
♦
Adjustable, Internal or External, Shared Reference
♦
Differential or Single-Ended Clock
♦
Accepts 25% to 75% Clock Duty Cycle
♦
User-Selectable DIV2 and DIV4 Clock Modes
♦
Power-Down Mode
♦
CMOS Outputs in Two’s Complement or Gray
Code
♦
Out-of-Range and Data-Valid Indicators
♦
Small, 68-Pin Thin QFN Package
♦
12-Bit Compatible Version Available (MAX12527)
♦
Evaluation Kit Available (Order MAX12557 EV Kit)
MAX12557
Ordering Information
PART
MAX12557ETK
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 Thin QFN-EP*
(10mm x 10mm x 0.8mm)
*EP
= Exposed paddle.
Selector Guide
PART
MAX12557
MAX12527
SAMPLING RATE
(Msps)
65
65
RESOLUTION
(Bits)
14
12
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 65Msps, 14-Bit, IF/Baseband ADC
MAX12557
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ................................................................-0.3V to +3.6V
OV
DD
to GND............-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
INAP, INAN to GND ...-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
INBP, INBN to GND ...-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
CLKP, CLKN to
GND ........................-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFIN, REFOUT
to GND ..................-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFAP, REFAN,
COMA to GND ......-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
REFBP, REFBN,
COMB to GND ......-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND .........-0.3V to the lower of (V
DD
+ 0.3V) and +3.6V
D0A–D13A, D0B–D13B, DAV,
DORA, DORB to GND..............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin Thin QFN 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ....................................4000mW
Operating Temperature Range................................-40°C to +85°C
Junction Temperature ...........................................................+150°C
Storage Temperature Range .................................-65°C to +150°C
Lead Temperature (soldering 10s).......................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -0.5dBFS (differen-
tial), DIFFCLK/SECLK
= OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 65MHz, T
A
= -40°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT (INAP, INAN, INBP, INBN)
Differential Input Voltage Range
Common-Mode Input Voltage
Analog Input Resistance
R
IN
C
PAR
Analog Input Capacitance
C
SAMPLE
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Data Latency
Figure 5
8
f
CLK
65
5
MHz
MHz
Clock
Cycles
dBFS
Switched capacitance,
each input, Figure 3
4.5
Each input, Figure 3
Fixed capacitance to ground,
each input, Figure 3
V
DIFF
Differential or single-ended inputs
±1.024
V
DD
/ 2
3.4
2
pF
V
V
kΩ
INL
DNL
f
IN
= 3MHz
f
IN
= 3MHz, no missing codes over
temperature (Note 2)
-1.0
14
±2.1
±0.6
±0.1
±0.5
+1.3
±0.9
±5.0
Bits
LSB
LSB
%FSR
%FSR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS (differential inputs)
Small-Signal Noise Floor
SSNF
Input at -35dBFS
f
IN
= 3MHz at -0.5dBFS
Signal-to-Noise Ratio
SNR
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
70.4
74.5
72.5
76
75
74.5
74.1
72.5
dB
2
_______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -0.5dBFS (differen-
tial), DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 65MHz, T
A
= -40°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
f
IN
= 3MHz at -0.5dBFS (Note 3)
Signal-to-Noise Plus Distortion
SINAD
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
f
IN
= 3MHz at -0.5dBFS (Note 3)
Spurious-Free Dynamic Range
SFDR
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
f
IN
= 3MHz at -0.5dBFS (Note 3)
Total Harmonic Distortion
THD
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
f
IN
= 3MHz at -0.5dBFS
Second Harmonic
HD2
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
f
IN
= 3MHz at -0.5dBFS
Third Harmonic
HD3
f
IN
= 32.5MHz at -0.5dBFS
f
IN
= 70MHz at -0.5dBFS
f
IN
= 175MHz at -0.5dBFS
Two-Tone Intermodulation
Distortion (Note 2)
f
IN1
= 68.5MHz at -7dBFS
f
IN2
= 71.5MHz at -7dBFS
f
IN1
= 172.5MHz at -7dBFS
f
IN2
= 177.5MHz at -7dBFS
f
IN1
= 68.5MHz at -7dBFS
f
IN2
= 71.5MHz at -7dBFS
f
IN1
= 172.5MHz at -7dBFS
f
IN2
= 177.5MHz at -7dBFS
f
IN1
= 68.5MHz at -7dBFS
f
IN2
= 71.5MHz at -7dBFS
f
IN1
= 172.5MHz at -7dBFS
f
IN2
= 177.5MHz at -7dBFS
Input at -0.2dBFS, -3dB rolloff
Figure 5
INAP = INAN = COMA
INBP = INBN = COMB
75.5
MIN
71.8
TYP
74.4
73.10
73.4
71.5
86.6
82.8
83.4
79.5
-84.5
-80.7
-81.7
-78.3
-89.5
-84.2
-84.7
-79.5
-93
-85.5
-86.5
-87.2
-88
dBc
-82.4
-91.5
dBc
-87.6
89
dBc
82.4
750
1.2
<0.15
1.02
MHz
ns
ps
RMS
LSB
RMS
dBc
dBc
-74.5
dBc
dBc
dB
MAX
UNITS
MAX12557
TTIMD
3rd-Order Intermodulation
Distortion
IM3
Two-Tone Spurious-Free
Dynamic Range
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Output Noise
SFDR
TT
FPBW
t
AD
t
AJ
n
OUT
_______________________________________________________________________________________
3
Dual, 65Msps, 14-Bit, IF/Baseband ADC
MAX12557
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -0.5dBFS (differen-
tial), DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 65MHz, T
A
= -40°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Overdrive Recovery Time
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Gain Matching
Offset Matching
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage
REFOUT Load Regulation
REFOUT Temperature Coefficient
REFOUT Short-Circuit Current
TC
REF
Short to V
DD
—sinking
Short to GND—sourcing
V
REFOUT
-1mA < I
REFOUT
< +1mA
2.000
2.048
35
±50
0.24
2.1
2.080
V
mV/mA
ppm/°C
mA
f
INA
or f
INB
= 70MHz at -0.5dBFS
f
INA
or f
INB
= 175MHz at -0.5dBFS
90
85
±0.01
±0.01
±0.1
dB
dB
%FSR
SYMBOL
CONDITIONS
±10% beyond full scale
MIN
TYP
1
MAX
UNITS
Clock
Cycle
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
V
REFAP
/V
REFAN
/V
COMA
and V
REFBP
/V
REFBN
/V
COMB
are generated internally)
REFIN Input Voltage
REFIN Input Resistance
COM_ Output Voltage
REF_P Output Voltage
REF_N Output Voltage
Differential Reference Voltage
Differential Reference
Temperature Coefficient
V
REFIN
R
REFIN
V
COMA
V
COMB
V
REFAP
V
REFBP
V
REFAN
V
REFBN
V
REFA
V
REFB
TC
REF
V
DD
/ 2
V
DD
/ 2 + (V
REFIN
x 3/8)
V
DD
/ 2 - (V
REFIN
x 3/8)
V
REFA
= V
REFAP
- V
REFAN
V
REFB
= V
REFBP
- V
REFBN
1.460
1.60
2.048
>50
1.65
2.418
0.882
1.536
±25
1.580
1.70
V
MΩ
V
V
V
V
ppm/°C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
REFAP
/V
REFAN
/V
COMA
and V
REFBP
/V
REFBN
/V
COMB
are applied
externally, V
COMA
= V
COMB
= V
DD
/ 2)
REF_P Input Voltage
REF_N Input Voltage
COM_ Input Voltage
Differential Reference Voltage
V
REFAP
V
REFBP
V
REFAN
V
REFBN
V
COM
V
REFA
V
REFB
V
REF_P
- V
COM
V
REF_N
- V
COM
V
DD
/ 2
V
REF_
= V
REF_P
- V
REF_N
= V
REFIN
x 3/4
+0.768
-0.768
1.65
1.536
V
V
V
V
4
_______________________________________________________________________________________
Dual, 65Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
L
≈
10pF at digital outputs, V
IN
= -0.5dBFS (differen-
tial), DIFFCLK/SECLK = OV
DD
, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
CLK
= 65MHz, T
A
= -40°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
REF_P Sink Current
REF_N Source Current
COM_ Sink Current
REF_P, REF_N Capacitance
COM_ Capacitance
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
Minimum Differential Clock Input
Voltage Swing
Differential Input Common-Mode
Voltage
CLK_ Input Resistance
CLK_ Input Capacitance
R
CLK
C
CLK
0.8 x
OV
DD
0.2 x
OV
DD
±5
±5
5
D0A–D13A, D0B–D13B, DORA, DORB:
I
SINK
= 200µA
DAV: I
SINK
= 600µA
D0A–D13A, D0B–D13B, DORA, DORB:
I
SOURCE
= 200µA
DAV: I
SOURCE
= 600µA
Tri-State Leakage Current
(Note 3)
I
LEAK
OV
DD
applied to input
Input connected to ground
OV
DD
-
0.2
V
OV
DD
-
0.2
±5
±5
µA
V
IH
V
IL
DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = OV
DD
DIFFCLK/SECLK = OV
DD
Each input, Figure 4
0.2
V
DD
/ 2
5
2
0.8 x
V
DD
0.2 x
V
DD
V
V
V
P-P
V
kΩ
pF
SYMBOL
I
REFAP
I
REFBP
I
REFAN
I
REFBN
I
COMA
I
COMB
C
REF_P
,
C
REF_N
C
COM_
CONDITIONS
V
REF_P
= 2.418V
V
REF_N
= 0.882V
V
COM_
= 1.65V
MIN
TYP
1.2
0.85
0.85
13
6
MAX
UNITS
mA
mA
mA
pF
pF
MAX12557
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)
Input High Threshold
Input Low Threshold
Input Leakage Current
Digital Input Capacitance
C
DIN
V
IH
V
IL
OV
DD
applied to input
Input connected to ground
V
V
µA
pF
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
Output-Voltage Low
V
OL
0.2
0.2
V
Output-Voltage High
V
OH
_______________________________________________________________________________________
5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
