CY25100
Field and Factory Programmable
Spread Spectrum Clock Generator for EMI Reduction
Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
■
Functional Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce EMI found in today’s high speed digital electronic
systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory or field-programmable
configuration memory array to synthesize output frequency,
spread percentage, crystal load capacitor, reference clock output
on/off, spread spectrum on/off function, and PD#/OE options.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range for
center spread is from ±0.25% to ±2.50%. The range for down
spread is from –0.5% to –5.0%.
The input to the CY25100 can either be a crystal or a clock
signal. The CY25100 has two clock outputs: REFCLK and
SSCLK. The non-spread spectrum REFCLK output has the
same frequency as the input of the CY25100.
For a complete list of related documentation, click
here.
Wide Operating Output (SSCLK) Frequency Range
❐
3 MHz to 200 MHz
Programmable Spread Spectrum with nominal 31.5 kHz
Modulation Frequency
❐
Center Spread: ±0.25% to ±2.5%
❐
Down Spread: –0.5% to –5.0%
Input frequency range
❐
External Crystal: 8 to 30 MHz Fundamental Crystals
❐
External Reference: 8 to 166 MHz Clock
Integrated Phase-Locked Loop (PLL)
Field Programmable devices available
Programmable Crystal Load Capacitor Tuning Array
Low Cycle-to-cycle Jitter
Spread Spectrum on/off function
Powerdown or Output Enable function
Commercial and Industrial temperature ranges
3.3 V operation
8-pin TSSOP and SOIC packages
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Logic Block Diagram
R FB
3
XIN
C
XIN
2
XOUT
C
XOUT
P LL
w ith
M O D U LA TIO N
C O N TR O L
PR O G R A M M A B LE
C O N FIG U R A TIO N
O U TP U T
D IVID E R S
and
MUX
6
R E FC LK
7
4
P D # or O E
8
S SO N #
SS C LK
1
VD D
5
V SS
Cypress Semiconductor Corporation
Document Number: 38-07499 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 10, 2016
CY25100
Contents
Pinouts .............................................................................. 3
Pin Description ................................................................. 3
User Specified Variables .................................................. 3
Programming Description ............................................... 4
Field Programmable CY25100 .................................. 4
CY3672 Programmer
and CY3690/CY3691 Socket Adapters .............................. 4
Factory Programmable CY25100 ................................ 4
Product Functions ............................................................ 4
Input Frequency (XIN, Pin 3 and XOUT, Pin 2) ........... 4
CXIN and CXOUT (Pin 3 and Pin 2) ........................... 4
Output Frequency (SSCLK, Pin 7) .............................. 4
Spread Percentage (SSCLK, Pin 7) ............................ 4
Reference Output (REFOUT, Pin 6) ............................ 4
Modulation Frequency ................................................. 4
Power Down or Output Enable (PD# or OE, Pin 4) ..... 4
Absolute Maximum Ratings ............................................ 5
Recommended Crystal Specifications ........................... 5
Operating Conditions ....................................................... 5
DC Electrical Characteristics .......................................... 6
Thermal Resistance .......................................................... 6
AC Electrical Characteristics .......................................... 7
Application Circuit ............................................................ 8
Switching Waveforms ...................................................... 9
Informational Graphs ..................................................... 10
Ordering Information ...................................................... 12
Possible Configurations ............................................. 12
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC®Solutions ....................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 38-07499 Rev. *L
Page 2 of 18
CY25100
Pinouts
Figure 1. 8-pin SOIC/TSSOP pinout
CY25100
1
2
VDD
XOUT
SSON# 8
SSCLK 7
REFCLK 6
3 XIN/CLKIN
4 PD#/OE
VSS 5
Pin Description
Pin
1
2
3
4
Name
VDD
XOUT
PD#/OE
Type
Power
Output
Input
3.3 V power supply.
Crystal output. Leave this pin floating if external clock is connected to pin 3.
Crystal input or reference clock input.
User has the option of choosing either PD# or OE function.
Power Down pin: Active LOW. If PD# = 0, PLL and crystal oscillator circuit are powered down,
and outputs are weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
Power supply ground.
Buffered reference output.
Spread spectrum clock output.
Spread spectrum control: Active LOW. 0 = spread on. 1 = spread off.
Description
XIN/CLKIN Input
5
6
7
8
VSS
REFCLK
SSCLK
SSON#
Power
Output
Output
Input
User Specified Variables
Pin Function
Pin Name
Pin#
Unit
Input Frequency
XIN and XOUT
3 and 2
MHz
USER
SPECIFIED
Total Crystal
Load
Capacitance
XIN and XOUT
3 and 2
pF
USER
SPECIFIED
Output
Frequency
SSCLK
7
MHz
USER
SPECIFIED
Spread Percent
(0.5% – 5%,
0.25% granularity)
SSCLK
7
% and Center- or
Down-spread
USER SPECIFIED
Reference
Output
REFOUT
6
On or Off
USER
SPECIFIED
Power Down or
Output Enable
PD#/OE
4
Select PD# or OE
USER
SPECIFIED
Document Number: 38-07499 Rev. *L
Page 3 of 18
CY25100
Programming Description
Field Programmable CY25100
The CY25100 is programmed at the package level, and must be
programmed prior to installation on a circuit board. Field
programmable devices are denoted by an “F” in the ordering
code, and are blank when shipped. The CY25100 is Flash
technology based, which allows it to be reprogrammed up to 100
times. This allows fast and easy design changes and product
updates, and eliminates issues with old and out of date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer with the CY3690 (TSSOP package) or
CY3691 (SOIC package) socket adapter.
programmable from 12 pF to 60 pF, in 0.5 pF increments.This
feature eliminates the need for external crystal load capacitors.
The following formula is used to calculate the value of C
XIN
and
C
XOUT
for matching the crystal load (C
L
):
C
XIN
= C
XOUT
= 2C
L
– C
P
where C
L
is the crystal load capacitor as specified by the crystal
manufacturer and C
P
is the parasitic PCB capacitance on each
node of the crystal.
For example, if a crystal with C
L
of 16 pF is used, and C
P
is 2 pF,
C
XIN
and C
XOUT
are calculated as:
C
XIN
= C
XOUT
= (2 × 16) – 2 = 30 pF
If using a driven reference, set C
XIN
and C
XOUT
to the minimum
value 12 pF, connect the reference to XIN/CLKIN, and leave
XOUT unconnected.
CY3672 Programmer and CY3690/CY3691 Socket
Adapters
The Cypress CY3672 programmer and the CY3690 or CY3691
socket adapter may be used to program field programmable
versions of the CY25100. The CY3690 enables users to program
the CY25100ZXCF and CY25100ZXIF (TSSOP). CY3691
provides the ability to program the CY25100SXCF and
CY25100SXIF (SOIC). The CY3690 and CY3691 are separate
orderable items, so the existing users of the CY3672
programmer need to order only the specific socket adapter to
program the CY25100.
Output Frequency (SSCLK, Pin 7)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is the
nominal value of the synthesized frequency without modulation
(spread percentage = 0). The range of synthesized clock is from
3 to 200 MHz.
Factory Programmable CY25100
Factory programming by Cypress is available for high volume
orders. All requests must be submitted to the local Cypress Field
Application Engineer (FAE) or sales representative. After the
request is processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number is used for additional sample requests and production
orders.
Spread Percentage (SSCLK, Pin 7)
The SSCLK spread can be programmed at any percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% for down spread.
Reference Output (REFOUT, Pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be programmed
to be enabled (clock on) or disabled (High Z, clock off). If this
output is not required, it is recommended that the disabled
(High Z, Clock Off) option be selected.
Product Functions
Input Frequency (XIN, Pin 3 and XOUT, Pin 2)
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signals
is 8 to 166 MHz.
Modulation Frequency
The modulation frequency is 31.5 kHz for all SSCLK frequencies
from 3 to 200 MHz.
C
XIN
and C
XOUT
(Pin 3 and Pin 2)
The CY25100 has internal load capacitors at Pin 3 (C
XIN
) and
Pin 2 (C
XOUT
) C
XIN
always equals C
XOUT
, and they are
Power Down or Output Enable (PD# or OE, Pin 4)
The part can be programmed to include either PD# or OE
function. PD# function powers down the oscillator and PLL. The
OE function disables the outputs.
Document Number: 38-07499 Rev. *L
Page 4 of 18
CY25100
Absolute Maximum Ratings
Supply Voltage (V
DD
) ...................................... –0.5 to +7.0 V
DC Input Voltage ................................ –0.5 V to V
DD
+ 0.5 V
Storage Temperature
(Non condensing) .................................... –55
C
to +125
C
Junction Temperature .............................. –40
C
to +125
C
Data Retention at Tj = 125
C
..............................> 10 years
Package Power Dissipation ..................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2000V
Recommended Crystal Specifications
Parameter
f
NOM
C
LNOM
R
1
R
3
/R
1
DL
Description
Nominal Crystal Frequency
Nominal Load Capacitance
Equivalent Series Resistance
(ESR)
Comments
Parallel resonance, fundamental
mode, AT cut
Internal load caps
Fundamental mode
Min
8
6
–
3
Typ
–
–
–
–
Max
30
30
25
–
Unit
MHz
pF
–
Ratio of Third Overtone Mode
Ratio used because typical R
1
ESR to Fundamental Mode ESR values are much less than the
maximum spec
Crystal Drive Level
No external series resistor assumed
–
0.5
2
mW
Operating Conditions
Parameter
V
DD
T
A
C
LOAD
f
REF
f
SSCLK
f
REFCLK
f
MOD
t
PU
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Maximum Load Capacitance at Pin 6 and Pin 7
External Reference Crystal (Fundamental tuned crystals only)
External Reference Clock
SSCLK Output Frequency, C
LOAD
= 15 pF
REFCLK Output Frequency, C
LOAD
= 15 pF
Spread Spectrum Modulation Frequency
Power Up Time for all V
DD
’s to reach minimum specified voltage (power
ramp must be monotonic)
Description
Min
3.13
0
–40
–
8
8
3
8
30.0
0.05
Typ
3.30
–
–
–
–
–
–
–
31.5
–
Max
3.45
70
85
15
30
166
200
166
33.0
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
MHz
kHz
ms
Document Number: 38-07499 Rev. *L
Page 5 of 18
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