LNBH25L
LNB supply and control IC with step-up and I²C interface
Features
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Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receiver output
voltage specifications
Accurate built-in 22 kHz tone generator suits
widely accepted standards
22 kHz tone waveform integrity guaranteed
also at no load condition
Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
Overload and overtemperature internal
protection with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interfacing.
QFN24 (4 x 4 mm)
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Applications
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STB satellite receivers
TV satellite receivers
PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25L is a monolithic voltage regulator and
interface IC, assembled in QFN24 (4x4)
specifically designed to provide the 13/18 V
power supply and the 22 kHz tone signalling to
Table 1.
Device summary
Order code
LNBH25LPQR
Package
QFN24 (4 x 4)
Packaging
Tape and reel
February 2012
Doc ID 022634 Rev 2
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www.st.com
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Contents
LNBH25L
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
Data encoding by external DiSEqC™ envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1
6.2
6.3
6.4
6.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1
7.2
7.3
Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Doc ID 022634 Rev 2
LNBH25L
Contents
7.4
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 022634 Rev 2
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Block diagram
LNBH25L
1
Block diagram
Figure 1.
Block diagram
ADDR SCL SDA
LX
PWM CTRL
I2C Digital core
DSQIN
DAC
Drop control
Tone ctrl
Diagnostics
Protections
Isense
PGND
VUP
ISEL
Linear
Regulator
Voltage
reference
Gate ctrl
Current
Limit
selection
VOUT
GND
BYP VCC
AM10460v1
4/28
Doc ID 022634 Rev 2
LNBH25L
Application information
2
Application information
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (V
UP
) that let the integrated LDO post-regulator (generating the
13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
V
UP
- V
OUT
= 1 V typ.). The IC is also provided with an undervoltage lockout circuit that
disables the whole circuit when the supplied V
CC
drops below a fixed threshold (4.7 V
typically). The step-up converter soft-start function reduces the inrush current during
startup. The SS time is internally fixed at 4ms typ. to switch from 0 to 13 V and 6 ms typ. to
switch from 0 to 18 V.
2.1
DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:
1.
2.
3.
by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C tone control bits must be set: EXTM = TEN = 1.
by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this
case the I²C tone control bits must be set: EXTM=0 and TEN=1.
through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
2.2
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
OUT
pin, by using the
LNBH25L integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25L tone generator in
terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN
pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending
the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As
soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25L activates the 22 kHz tone on the V
OUT
output with about 1 µs delay from TTL
signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
has expired (refer to
Figure 2).
Figure 2.
Tone enable and disable timing (using external waveform)
DSQIN
~ 1 µs
Tone
Output
AM10426v1
~ 60 µs
Doc ID 022634 Rev 2
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