Low Skew, 1-to-6, Crystal Oscillator/LVCMOS-
TO-3.3V, 2.5V LVPECL/LVCMOS Fanout Buffer
G
ENERAL
D
ESCRIPTION
T h e 8 5 3 6 I - 3 3 i s a l o w s k e w, h i g h p e r f o r m a n c e
1-to-6 Crystal Oscillator/LVCMOS-to-3.3V, 2.5V LVPECL/
LVCMOS fanout buffer. The 8536I-33 has selectable sin-
gle ended clock or crystal inputs. The single-ended clock
input accepts LVCMOS or LVTTL input levels and translate
them to 3.3V LVPECL levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the 8536I-33 ideal for those applications demanding well
defined performance and repeatability.
8536I-33
DATA SHEET
F
EATURES
•
Three differential LVPECL outputs, and
three single ended LVCMOS outputs
•
Selectable LVCMOS/LVTTL CLK or crystal inputs
•
CLK can accept the following input levels: LVCMOS, LVTTL
•
Crystal frequency: 25MHz
•
Maximum output frequency: 266MHz
•
Output skew: 80ps (maximum)
•
Part-to-part skew: 800ps (maximum)
•
Propagation delay: 1.95ns (maximum)
•
Additive phase jitter, RMS: 0.32ps (typical), LVPECL output
•
Full 3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
CLK_EN
Pullup
P
IN
A
SSIGNMENT
D
LE
CLK
Pulldown
0
LVPECL
Q0
nQ0
25MHz
XTAL_IN
OSC
XTAL_OUT
CLK_SEL
Pullup
1
Q1
nQ1
Q2
nQ2
8536I-33
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
LVCMOS
Q3
Q4
Q5
8536I-33 REVISION B 7/10/15
1
©2015 Integrated Device Technology, Inc.
8536I-33 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2,
3
4
5
6
7, 15,
20
8, 9
10
11, 12
13, 14
16, 18, 19
17
V
Name
CLK_EN
XTAL_IN,
XTAL_OUT
V
CC
Type
Input
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Power
Pullup
Description
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ0 output is forced high. LVCMOS
/ LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Positive supply pins.
CLK
CLK_SEL
V
EE
Pulldown Single-ended clock input. LVCMOS / LVTTL interface levels.
Pullup
Clock select input. When HIGH, selects XTAL inputs.
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential clock outputs. LVPECL interface levels.
Output power supply mode for LVPECL clock outputs.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Single ended clock outputs. LVCMOS / LVTTL interface levels.
Output power supply mode for LVCMOS / LVTTL clock outputs.
Q0, nQ0
CCO_LVPECL
Q1, nQ1
nQ2, Q2
Q3, Q4, Q5
V
CCO_LVCMOS
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Q3:Q5
Q3:Q5
V
CC,
V
CCO_LVCMOS
= 3.465V
V
CC,
V
CCO_LVCMOS
= 2.625V
Q3:Q5
V
CC,
V
CCO_LVCMOS
= 3.465V
V
CC,
V
CCO_LVCMOS
= 2.625V
Test Conditions
Minimum
Typical
4
8
5
51
51
15
20
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
Ω
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-
3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
2
REVISION B 7/10/15
8536I-33 DATA SHEET
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Source
CLK
XTAL_IN, XTAL_OUT
CLK
Q0:Q2
Disabled; LOW
Disabled; LOW
Enabled
Outputs
nQ0:nQ2
Disabled; HIGH
Disabled; HIGH
Enabled
Q3:Q5
Disabled; LOW
Disabled; LOW
Enabled
Enabled
1
1
XTAL_IN, XTAL_OUT
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or
crystal oscillator edge as shown in
Figure
1.
In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
Q0:Q2
LOW
HIGH
Outputs
nQ0:nQ2
HIGH
LOW
Q3:Q5
LOW
HIGH
REVISION B 7/10/15
3
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-
3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
8536I-33 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
(LVCMOS)
Outputs, V
O
(LVCMOS)
Inputs, V
I
(LVPECL)
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO_LVCMOS
+ 0.5V
-0.5V to V
CC
+ 0.5V
50mA
100mA
91.1°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVPECL
= V
CCO_LVCMOS
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCO_LVPECL,
V
CCO_LVCMOS
I
EE
I
CCO_LVPECL
I
CCO_LVCMOS
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
80
25
45
Units
V
V
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVPECL
= V
CCO_LVCMOS
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCO_LVPECL,
V
CCO_LVCMOS
I
EE
I
CCO_LVPECL
I
CCO_LVCMOS
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
80
30
45
Units
V
V
mA
mA
mA
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-
3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
4
REVISION B 7/10/15
8536I-33 DATA SHEET
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
V
HYS
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input Hysteresis
Input
High Current
Input
Low Current
CLK_EN, CLK_
SEL
CLK
CLK_EN, CLK_
SEL
CLK
CLK_EN, CLK_
SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CCO_LVCMOS
= 3.465V
V
CCO_LVCMOS
= 2.625V
V
CCO_LVCMOS
= 3.465 or 2.625V
-5
-150
2.6
1.8
0.5
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
Minimum
2
1.7
-0.3
-0.3
100
150
5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
Units
V
V
V
V
mV
µA
µA
µA
µA
V
V
V
I
IL
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
CCO_LVCMOS
/2. See Parameter Measurement Information Section. “LVCMOS Output Load
Test circuit” diagrams.
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVPECL
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_LVPECL
- 1.4
V
CCO_LVPECL
- 2.0
0.6
Typical
Maximum
V
CCO_LVPECL
- 0.9
V
CCO_LVPECL
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO_LVPECL
- 2V.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVPECL
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_LVPECL
- 1.4
V
CCO_LVPECL
- 2.0
0.4
Typical
Maximum
V
CCO_LVPECL
- 0.9
V
CCO_LVPECL
- 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO_LVPECL
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
12
Test Conditions
Minimum Typical Maximum
Fundamental
40
50
7
1
MHz
Units
Ω
pF
mW
REVISION B 7/10/15
5
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-
3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
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