Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30W termination resistors (3-State)
74ALVT162821
FEATURES
•
Outputs include series resistance of 30W making external
termination resistors unnecessary
DESCRIPTION
The 74ALVT162821 high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive. It is designed for V
CC
operation at 2.5V or 3.3V with I/O
compatibility to 5V.
The 74ALVT162821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (nOE) controls all ten 3-State buffers
independent of the register operation. When nOE is Low, the data in
the register appears at the outputs. When nOE is High, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
The 74ALVT162821 is designed with 30W series resistance in both
High and Low output stages. This design reduces the line noise in
applications such as memory address drivers, clock drivers and bus
receivers/transmitters. The series termination resistors reduce
overshoot and undershoot and are ideal for driving memory arrays.
•
20-bit positive-edge triggered register
•
5V I/O Compatible
•
Multiple V
CC
and GND pins minimize switching noise
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
Output capability
+12mA/-12mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
•
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nCP to nQ
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C
C
L
= 50pF
V
I
= 0V or V
CC
V
O
= 0 or V
CC
Outputs disabled
TYPICAL
UNIT
2.5V
4.4
3.8
3
9
40
3.3V
3.2
3.2
3
9
70
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT162821 DL
74ALVT162821 DGG
NORTH AMERICA
AV162821 DL
AV162821 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 Oct 02
2
853-2041 20127
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30W termination resistors (3-State)
74ALVT162821
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49,
48, 47, 45, 44, 43,
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10,
12, 13, 14,
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32,
39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 - 1D9
2D0 - 2D9
FUNCTION
FUNCTION TABLE
INPUTS
nOE
Data inputs
L
L
L
1Q0 - 1Q9
2Q0 - 2Q9
Data outputs
nCP
↑
↑
↑
nDx
l
h
X
INTERNAL
REGISTER
L
H
NC
OUTPUTS
nQ0 - nQ9
L
H
NC
OPERATING
MODE
Load and read
register
Hold
1OE, 2OE
1CP, 2CP
GND
V
CC
Output enable inputs
(active-Low)
Clock pulse inputs
(active rising edge)
Ground (0V)
Positive supply
voltage
H
↑
X
NC
Z
Disable
↑
H
Dn
Dn
Z
outputs
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High
clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑
= Low to High clock transition
↑
= Not a Low-to-High clock transition
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00004
1998 Oct 02
4
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30W termination resistors (3-State)
74ALVT162821
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–1.2 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
2.5V RANGE LIMITS
MIN
2.3
0
1.7
0.7
–8
12
10
+85
–40
MAX
2.7
5.5
3.3V RANGE LIMITS
MIN
3.0
0
2.0
0.8
–12
12
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
1998 Oct 02
5
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
