DISCRETE SEMICONDUCTORS
DATA SHEET
handbook, halfpage
MBD128
BF1204
Dual N-channel dual gate
MOS-FET
Product specification
Supersedes data of 2001 Apr 25
2010 Sep 16
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES
Two low noise gain controlled amplifiers in a single
package
Superior cross-modulation performance during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
Gain controlled low noise amplifiers for VHF and UHF
applications with 3 to 9 V supply voltage, such as digital
and analog television tuners and professional
communications equipment.
DESCRIPTION
The BF1204 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected. Internal bias
circuits enable DC stabilization and a very good
cross-modulation performance during AGC. Integrated
diodes between the gates and source protect against
excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
PINNING - SOT363
PIN
1
2
3
4
5
6
gate 1 (a)
gate 2
gate 1 (b)
drain (b)
source
drain (a)
BF1204
DESCRIPTION
handbook, halfpage
6
5
4
d (a)
s
d (b)
AMP
a
AMP
b
1
2
3
g1 (a)
g2
g1 (b)
MBL252
Top view
Marking code: L3*
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
T
s
102
C;
note 1
I
D
= 12 mA; f = 1 MHz
I
D
= 12 mA; f = 1 MHz
f = 1 MHz
f = 800 MHz
25
TYP.
30
1.7
15
1.1
105
MAX.
UNIT
Per MOS-FET; unless otherwise specified
V
DS
I
D
P
tot
y
fs
C
ig1-s
C
rss
NF
X
mod
T
j
Note
1. T
s
is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2010 Sep 16
2
drain-source voltage
drain current (DC)
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
cross-modulation
operating junction temperature
10
30
200
40
2.2
1.8
150
V
mA
mW
mS
pF
fF
dB
dBV
C
input level for k = 1% at 40 dB AGC 100
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
T
s
102
C
65
MIN.
BF1204
MAX.
UNIT
Per MOS-FET; unless otherwise specified
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
drain-source voltage
drain current (DC)
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
10
30
10
10
200
+150
150
V
mA
mA
mA
mW
C
C
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
PARAMETER
thermal resistance from junction to soldering point
VALUE
240
UNIT
K/W
handbook, halfpage
250
MGS359
Ptot
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
2010 Sep 16
3
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
STATIC CHARACTERISTICS
T
j
= 25
C;
per MOS-FET; unless otherwise specified.
SYMBOL
V
(BR)DSS
PARAMETER
CONDITIONS
V
GS
= V
DS
= 0; I
G1-S
= 10 mA
V
GS
= V
DS
= 0; I
G2-S
= 10 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 100
A
V
DS
= 5 V; V
G1-S
= 4 V; I
D
= 100
A
V
G2-S
= 4 V; V
DS
= 5 V; R
G
= 120 k; note 1
V
G1-S
= 5 V; V
G2-S
= V
DS
= 0
V
G2-S
= 4 V; V
G1-S
= V
DS
= 0
MIN.
10
6
6
0.5
0.5
0.3
0.3
8
BF1204
MAX.
10
10
1.5
1.5
1
1.2
16
50
20
UNIT
V
V
V
V
V
V
V
mA
nA
nA
drain-source breakdown voltage V
G1-S
= V
G2-S
= 0; I
D
= 10
A
V
(BR)G1-SS
gate-source breakdown voltage
V
(BR)G2-SS
gate-source breakdown voltage
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-S
I
G2-S
Note
1. R
G1
connects gate 1 to V
GG
= 5 V.
DYNAMIC CHARACTERISTICS
forward source-gate voltage
forward source-gate voltage
gate-source threshold voltage
gate-source threshold voltage
drain-source current
gate cut-off current
gate cut-off current
Common source; T
amb
= 25
C;
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 12 mA; per MOS-FET
(1)
; unless otherwise specified.
SYMBOL
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
G
tr
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
reverse transfer capacitance
power gain
T
j
= 25
C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 200 MHz; G
S
= 2 mS; B
S
= B
S(opt)
;
G
L
= 0.5 mS; B
L
= B
L(opt)
; note 1
f = 400 MHz; G
S
= 2 mS; B
S
= B
S(opt)
;
G
L
= 1 mS; B
L
= B
L(opt)
; note 1
CONDITIONS
MIN.
25
30
26
TYP.
30
1.7
3.3
0.85
15
34
30
25
9
0.9
1.1
92
105
MAX.
40
2.2
38
34
29
11
1.5
1.8
UNIT
mS
pF
pF
pF
fF
dB
dB
dB
dB
dB
dB
dBV
dBV
dBV
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
S(opt)
; 21
G
L
= 1 mS; B
L
= B
L(opt)
; note 1
NF
noise figure
f = 10.7 MHz; G
S
= 20 mS; B
S
= 0
f = 400 MHz; Y
S
= Y
S(opt)
f = 800 MHz; Y
S
= Y
S(opt)
X
mod
cross-modulation
input level for k = 1% at 0 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; note 2
input level for k = 1% at 10 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; note 2
input level for k = 1% at 40 dB AGC;
f
w
= 50 MHz; f
unw
= 60 MHz; note 2
Notes
1. For the MOS-FET not in use: V
G1-S
= 0; V
DS
= 0.
2. Measured in Fig.19 test circuit.
2010 Sep 16
4
90
100
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
ALL GRAPHS FOR ONE MOS-FET
MCD952
BF1204
handbook, halfpage
20
ID
VG2-S
=
4 V
3.5 V
3V
2.5 V
handbook, halfpage
24
MCD953
(mA)
16
2V
ID
(mA)
16
VG1-S
=
1.5 V
1.4 V
1.3 V
12
8
1.5 V
8
1.2 V
1.1 V
1V
4
1V
0
0
0.4
0.8
1.2
1.6
2
VG1-S (V)
0.9 V
0
0
2
4
6
8
10
VDS (V)
V
DS
= 5 V.
T
j
= 25
C.
V
G2-S
= 4 V.
T
j
= 25
C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
handbook, halfpage
100
MCD954
IG1
(μA)
VG2-S
=
4 V
3.5 V
3V
handbook, halfpage
40
MCD955
yfs
(mS)
30
VG2-S
=
4 V
3.5 V
80
3V
60
2.5 V
20
2.5 V
40
2V
10
20
1.5 V
0
0
0.5
1
1.5
1V
2
2.5
VG1-S (V)
2V
0
0
4
8
12
16
20
ID (mA)
V
DS
= 5 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
Fig.5
Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6
Forward transfer admittance as a function
of drain current; typical values.
2010 Sep 16
5
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