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74AC175 • 74ACT175 Quad D-Type Flip-Flop
November 1988
Revised November 1999
74AC175 • 74ACT175
Quad D-Type Flip-Flop
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D-type inputs is stored during the LOW-to-HIGH clock tran-
sition. Both true and complemented outputs of each flip-
flop are provided. A Master Reset input resets all flip-flops,
independent of the Clock or D-type inputs, when LOW.
Features
s
I
CC
reduced by 50%
s
Edge-triggered D-type inputs
s
Buffered positive edge-triggered clock
s
Asynchronous common reset
s
True and complement output
s
Outputs source/sink 24 mA
s
ACT175 has TTL-compatible inputs
Ordering Code:
Order Number
74AC175SC
74AC175SJ
74AC175MTC
74AC175PC
74ACT175SC
74ACT175SJ
74ACT175MTC
74ACT175PC
Package Number
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
3
CP
MR
Q
0
–Q
3
Q
0
–Q
3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009936
www.fairchildsemi.com
74AC175 • 74ACT175
Functional Description
The AC/ACT175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the state of their individual D inputs on the LOW-
to-HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH indepen-
dent of Clock or Data inputs. The AC/ACT175 is useful for
general logic applications where a common Master Reset
and Clock are acceptable.
Truth Table
Inputs
@ t
n
, MR
=
H
D
n
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
t
n
=
Bit Time before Clock Pulse
t
n+1
=
Bit Time after Clock Pulse
Outputs
@ t
n+1
Q
n
L
H
Q
n
H
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74AC175 • 74ACT175
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
140°C
±
50 mA
−65°C
to
+150°C
±
50 mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
CC
(Note 4)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
4.0
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
V
IN
=
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
IN
=
V
IL
or V
IH
0.44
0.44
0.44
±
1.0
75
−75
40.0
µA
mA
mA
µA
V
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
OUT
=
50
µA
V
I
OH
= −12
mA
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3
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74AC175 • 74ACT175
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current(Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
4.0
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
1.5
75
−75
40.0
µA
mA
mA
mA
µA
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 5)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 5)
V
I
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
CC
Symbol
f
MAX
t
PLH
Maximum Clock
Frequency
Propagation Delay
CP to Q
n
or Q
n
t
PHL
Propagation Delay
CP to Q
n
or Q
n
t
PLH
Propagation Delay
MR to Q
n
t
PHL
Propagation Delay
MR to Q
n
Note 7:
Voltage Range 3.3 is 3.3V
±
0.3V
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Min
149
187
2.0
1.5
2.5
1.5
3.0
2.0
3.0
2.0
Typ
214
244
9.5
7.0
8.5
6.0
7.5
5.5
8.5
6.0
12.0
9.0
13.0
9.5
12.5
9.0
11.0
8.5
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
139
187
2.0
1.0
2.0
1.5
2.5
1.5
2.5
1.5
13.5
9.5
14.5
10.5
13.5
10.0
12.5
9.0
ns
ns
ns
ns
Max
MHz
Units
Parameter
(V)
(Note 7)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
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4
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