Datasheet
ISL70005SEH, ISL73005SEH
Radiation Hardened Dual Output Point-of-Load, Integrated Synchronous Buck and Low Dropout
Regulator
The
ISL70005SEH
and
ISL73005SEH
are radiation
hardened dual output Point-of-Load (POL) regulators
combining the high efficiency of a synchronous buck
regulator with the low noise of a Low Dropout (LDO)
regulator. They are suited for systems with 3.3V or 5V
power buses and can support continuous output load
currents of 3A for the buck regulator and ±1A for the
LDO.
The buck regulator uses a voltage mode control
architecture and switches at a resistor adjustable
frequency of 100kHz to 1MHz. Externally adjustable
loop compensation allows for an optimum balance
between stability and output dynamic performance.
The internal synchronous power switches are
optimized for high efficiency and excellent thermal
performance.
The LDO is completely configurable independent of
the switching regulator. It uses NMOS pass devices
and separate chip bias voltage (L_VCC) to drive its
gate, enabling the LDO to operate with a very low
voltage at the L_VIN input. The LDO can sink and
source up to 1A continuously, making it an ideal
choice to power DDR memory.
The ISL70005SEH and ISL73005SEH are available
in a space saving 28 Ld ceramic dual flat-pack
package or in die form. They are specified to operate
across a temperature range of T
A
= -55°C to +125°C.
Features
• Dual output regulator: sync buck and LDO
• Independent EN, SS, and PG indicators
• ±1% reference voltage
• 1A current sourcing/sinking capability on LDO
• External clock synchronization: 100kHz to 1MHz
• Full military temperature range operation
○
T
A
= -55°C to +125°C
○
T
J
= -55°C to +150°C
• Radiation acceptance testing - ISL70005SEH
○
HDR (50-300rad(Si)/s): 100krad(Si)
○
LDR (0.01rad(Si)/s): 75krad(Si)
• Radiation acceptance testing - ISL73005SEH
○
LDR (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (see test report)
○
No SEB or SEL at LET 86.4MeV•cm
2
/mg
○
SET at LET 86.4MeV•cm
2
/mg <±3%
ΔV
OUT
○
No SEFI at LET 43MeV•cm
2
/mg
• Electrically screened to DLA SMD
5962-19209
Applications
• Point-of-load for low power FPGA core, auxiliary
and I/O supply voltages
• DDR memory power for VDDQ and VTT rails
• Distributed power system of satellite payloads
Related Literature
For a full list of related documents visit our website:
•
ISL70005SEH, ISL73005SEH
device pages
ISL70005SEH, ISL73005SEH
Buck Regulator
3.3V or 5V
B_PVINx
B_LXx
VDDQ = 1.8V
0.915
0.910
VDDQ
L_VIN
L_OUT
VTT = 0.9V
LDO Voltage (V)
0.905
0.900
0.895
0.890
-1.5
L_VCC = B_VCC = 5V
L_VIN = 1.8V
L_EA+ = 0.9V
-1.0
-0.5
0.0
0.5
1.0
1.5
LDO Regulator
DDR Memory
Controller
R
S
R
T
DDR
Memory
LDO Current (A)
Figure 1. Power Solution for DDR2 Memory
Figure 2. LDO Load Regulation; DDR2 Configuration
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 1 of 46
ISL70005SEH, ISL73005SEH
Contents
1.
1.1
1.2
1.3
1.4
1.5
2.
2.1
2.2
2.3
2.4
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6.
6.1
6.2
6.3
6.4
6.5
7.
7.1
7.2
8.
8.1
8.2
8.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
7
7
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Dropout Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
28
29
30
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Supply Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Selection and External Sync for Buck Regulator. . . . . . . . . . . . . . . . . . . . . . . .
B_EN and L_EN Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start Capacitor for Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start Capacitor for LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Independent Output Point-of-Load Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDO Tracking Buck for DDR Memory Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
32
32
32
32
Synchronous Buck Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Buck Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Feedback Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
35
36
LDO Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LDO Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LDO Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Buck Regulator PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LDO Regulator PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Example PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 2 of 46
ISL70005SEH, ISL73005SEH
9.
10.
11.
12.
Die and Assembly Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Metalization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 3 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1.
1.1
Overview
Typical Application Schematics
VIN = 3.3V
ISL70005S EH
1
2
3
4
VIN = 3.3V
From FPGA
5
6
7
8
9
From I/O Port
From I/O Port
VIN = 3.3V
10
11
12
13
14
B_SS
B_FB
B_COMP
B_RT
B_VCC
L_PG
28
to FPG A
to FPG A
VIN = 3.3V
V
CORE
= 1.8V
+
B_PG 27
B_VIN2
B_LX2
B_PGND2
26
25
24
23
22
21
20
19
18
17
16
15
RF
VIN = 3.3V
VIN = 3.3V
B_SYNC B_PGND1
B_GND1
B_GND2
VREF
B_EN
L_EN
L_VCC
L_SS
L_EA+
B_LX1
B_VIN1
TEST
L_VIN
L_OUT
L_PGND
L_GND
L_EA-
R4
R1
V
I/O
= 1.5V
RG
Figure 3. ISL70005SEH Application for Low Power FPGA Core and I/O Supply
VIN = 3.3V
ISL70005S EH
1
2
3
4
VIN = 3.3V
From FPGA
5
6
7
8
9
From I/O Port
From I/O Port
VIN = 3.3V
10
11
12
13
14
B_SS
B_FB
B_COMP
B_RT
B_VCC
L_PG
B_PG
B_VIN2
B_LX2
B_PGND2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RG
VDDQ = 1.8 V
VTT = 0.9V (Tra cks VDDQ)
VIN = 3.3V
R4
R1
VIN = 3.3V
VDDQ = 1.8 V
+
to I/O P ort
to I/O P ort
B_SYNC B_PGND1
B_GND1
B_GND2
VREF
B_EN
L_EN
L_VCC
L_SS
L_EA+
B_LX1
B_VIN1
TEST
L_VIN
L_OUT
L_PGND
L_GND
L_EA-
RF
VDDQ/2
Figure 4. ISL70005SEH Application for DDR Memory Power Solution
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 4 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1.2
Functional Block Diagram
B_PG
B_RT
B_SYNC
B_VCC
B_GND1,
B_GND2
B_VIN1 ,
B_VIN2
B_VCC
B_VCC
PGO OD
Logic
Osc illa tor and Clock
Generator
SHDNB
B_GND
B_VCC
SHDN
B
B_VCC
B_COMP
B_VCC
B_FB
PWM Control Logic,
Gat e Drive and
Ove rcurre nt Lim it
VREF
L_VCC
B_VCC
VREF
600 mV
L_VCC
THE RMAL
SENSE
B_EN
L_EN
L_PG
SHDNL
L_VCC
SHDNL
PGO OD
Logic
L_VCC
UVLO and Shutdown
Logic
SHDNB
+ Current
Sense
B_LX1,
B_LX2
I
SS
B_SS
B_VCC
L_VCC
B_PGND1,
B_PGND2
L_VCC
Source
I_SENSE
L_VIN
L_VCC
L_OUT
B_GND
Ove rcurre nt
Lim it
L_GND
L_VCC
L_PGND
Sink
I_SENSE
L_PGND
I
SS
B_PGND
L_VCC
L_GND
L_EA- L_EA+
L_SS
L_VCC
L_GND
Figure 5. Block Diagram
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 5 of 46
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