Am29F032B
Data Sheet
Am29F032B Cover Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21610
Revision
D
Amendment
8
Issue Date
November 11, 2009
D at a
S hee t
This page left intentionally blank.
2
Am29F032B
21610_D8 November 11, 2009
DATA SHEET
Am29F032B
32 Megabit (4 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
■
Manufactured on 0.32 µm process technology
■
High performance
— Access times as fast as 70 ns
■
Low power consumption
— 30 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current (standard access
time to active mode)
■
Flexible sector architecture
— 64 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
— A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
— Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■
Minimum 1,000,000 write/erase cycles
guaranteed
■
20-year data retention at 125° C
— Reliable operation for the life of the system
■
Package options
— 40-pin TSOP
— 44-pin SO
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■
Ready/Busy output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■
Erase Suspend/Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■
Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21610
Rev:
D
Amendment:
8
Issue Date:
November 11, 2009
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
memory organized as 4,194,304 bytes of 8 bits each.
The 4 Mbytes of data are divided into 64 sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F032B is offered
in 40-pin TSOP and 44-pin SO packages. The
Am29F032B is manufactured using AMD’s 0.32 µm
process technology. This device is designed to be pro-
grammed in-system with the standard system 5.0 volt
V
CC
supply. A 12.0 volt V
PP
is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
The standard device offers access times of 70 and 90
ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for
the programming and erase operations. Reading data
out of the device is similar to reading from 12.0 volt
Flash or EPROM devices.
The device is programmed by executing the program
command sequence. This invokes the Embedded Pro-
gram algorithm—an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin. The device is erased by executing
the erase command sequence. This invokes the Em-
bedded Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. A sector is typically
erased and verified within one second. The device is
erased when shipped from the factory.
The hardware sector group protection feature disables
both program and erase operations in any combination
of the eight sector groups of memory. A sector group
consists of four adjacent sectors.
The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
True background erase can thus be achieved.
The device requires only a single 5.0 volt power supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. A low V
CC
detector automati-
cally inhibits write operations during power transitions.
The host system can detect whether a program or
erase cycle is complete by using the RY/BY# pin, the
DQ7 (Data# Polling) or DQ6 (toggle) status bits. After
a program or erase cycle has been completed, the de-
vice automatically returns to the read mode.
A hardware RESET# pin terminates any operation in
progress. The internal state machine is reset to the
read mode. The RESET# pin may be tied to the sys-
tem reset circuitry. Therefore, if a system reset occurs
during either an Embedded Program or Embedded
Erase algorithm, the device is automatically reset to the
read mode. This enables the system’s microprocessor
to read the boot-up firmware from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at
a time using the programming mechanism of hot
electron injection.
2
Am29F032B
21610D8 November 11, 2009
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
Requirements for Reading Array Data .....................................
Writing Commands/Command Sequences ..............................
Program and Erase Operation Status ......................................
Standby Mode ..........................................................................
RESET#: Hardware Reset Pin .................................................
Output Disable Mode................................................................
4
4
5
6
6
7
8
8
8
9
9
9
9
DQ2: Toggle Bit II ...................................................................
Reading Toggle Bits DQ6/DQ2...............................................
DQ5: Exceeded Timing Limits ................................................
DQ3: Sector Erase Timer .......................................................
19
19
20
20
Figure 5. Toggle Bit Algorithm........................................................ 20
Table 6. Write Operation Status..................................................... 21
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negative Overshoot Waveform ...................... 22
Figure 7. Maximum Positive Overshoot Waveform........................ 22
Table 1. Am29F032B Device Bus Operations .................................. 8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible.................................................................. 23
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup...................................................................... 24
Table 7. Test Specifications ........................................................... 24
Table 2. Am29F032B Sector Address Table................................... 10
Autoselect Mode..................................................................... 11
Table 3. Am29F032B Autoselect Codes ......................................... 11
Sector Group Protection/Unprotection.................................... 12
Table 4. Sector Group Addresses................................................... 12
Key To Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Read-only Operations............................................................. 25
Figure 9. Read Operation Timings ................................................. 25
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Temporary Sector Group Unprotect Operation................ 12
Hardware Reset (RESET#) .................................................... 26
Figure 10. RESET# Timings .......................................................... 26
Hardware Data Protection ...................................................... 13
Low VCC Write Inhibit..................................................................... 13
Write Pulse “Glitch” Protection........................................................ 13
Logical Inhibit .................................................................................. 13
Power-Up Write Inhibit .................................................................... 13
Write (Erase/Program) Operations ......................................... 27
Figure 11. Program Operation Timings..........................................
Figure 12. Chip/Sector Erase Operation Timings ..........................
Figure 13. Data# Polling Timings (During Embedded Algorithms).
Figure 14. Toggle Bit Timings (During Embedded Algorithms)......
Figure 15. DQ2 vs. DQ6.................................................................
28
29
30
30
31
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data ................................................................ 13
Reset Command..................................................................... 13
Autoselect Command Sequence ............................................ 14
Byte Program Command Sequence....................................... 14
Chip Erase Command Sequence ........................................... 14
Figure 2. Program Operation .......................................................... 15
Temporary Sector Unprotect .................................................. 31
Figure 16. Temporary Sector Group Unprotect Timings ................ 31
Write (Erase/Program) Operations—Alternate CE#
Controlled Writes .................................................................... 32
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33
Sector Erase Command Sequence ........................................ 15
Erase Suspend/Erase Resume Commands........................... 15
Figure 3. Erase Operation............................................................... 16
Table 5. Am29F032B Command Definitions................................... 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18
DQ7: Data# Polling................................................................. 18
Figure 4. Data# Polling Algorithm ................................................... 18
DQ6: Toggle Bit I .................................................................... 19
Erase And Programming Performance . . . . . . . 34
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34
TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35
SO 044–44-Pin Small Outline Package.................................. 35
TS 040–40-Pin Standard Thin Small Outline Package........... 36
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 37
November 11, 2009 21610D8
Am29F032B
3
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