S i 5 1 0 / 5 11
C
R YS TA L
O
SCILLATOR
(XO) 100 kH
Z
Features
TO
250 MH
Z
Supports any frequency from
100 kHz to 250 MHz
Low jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5 x 7, 3.2 x 5,
and 2.5 x 3.2 mm packages
Pb-free, RoHS compliant
–40
to 85
o
C operation
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Ordering Information:
See page 14.
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation
Pin Assignments:
See page 12.
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
OE
1
4
V
DD
GND
2
3
CLK
Si510 (CMOS)
NC
OE
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Functional Block Diagram
V
DD
OE
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
OE
OE
1
1
2
2
3
3
6
6
5
5
4
4
V
DD
V
DD
CLK–
CLK–
CLK+
CLK+
Low Noise Regulator
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
DSPLL
®
Synthesis
CLK+
CLK–
NC
NC
GND
GND
GND
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
Si510/511
Rev. 1.3 12/17
Copyright © 2017 by Silicon Laboratories
Si510/511
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
Rev. 1.3
Si510/511
1. Electrical Specifications
Table 1. Operating Specifications
Parameter
Supply Voltage
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
21
Max
3.63
2.75
1.89
26
Unit
V
V
V
mA
Supply Current
I
DD
CMOS, 100 MHz,
single-ended
LVDS
(output enabled)
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
—
—
—
—
0.80 x V
DD
—
—
19
39
41
—
—
—
45
23
43
44
18
—
0.20 x V
DD
—
mA
mA
mA
mA
V
V
k
o
OE "1" Setting
OE "0" Setting
OE Internal Pull-Up/Pull-
Down Resistor
*
Operating Temperature
V
IH
V
IL
R
I
T
A
See Note
See Note
–40
—
85
C
*Note:
Active high and active low polarity OE options available. Active high option includes an internal pull-up.
Active low option includes an internal pull-down. See ordering information on page 14.
Rev. 1.3
3
Si510/511
Table 2. Output Clock Frequency Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Nominal Frequency
Symbol
F
O
F
O
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Min
0.1
0.1
–30
–50
–100
–20
–25
–50
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
212.5
250
+30
+50
+100
+20
+25
+50
10
5
40
20
60
Unit
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ms
µs
µs
µs
µs
Total Stability*
Temperature Stability
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Startup Time
Disable Time
T
SU
T
D
Minimum V
DD
until output
frequency (F
O
) within specification
F
O
10 MHz
F
O
< 10 MHz
Enable Time
T
E
F
O
10 MHz
F
O
< 10 MHz
*Note:
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40
o
C.
4
Rev. 1.3
Si510/511
Table 3. Output Clock Levels and Symmetry
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
CMOS Output Logic
High
CMOS Output Logic
Low
CMOS Output Logic
High Drive
Symbol
V
OH
V
OL
I
OH
Test Condition
Min
0.85 x V
DD
—
Typ
—
—
—
—
—
—
—
—
0.8
0.6
—
Max
—
0.15 x V
DD
—
—
—
—
—
—
1.2
0.9
565
Unit
V
V
mA
mA
mA
mA
mA
mA
ns
ns
ps
3.3 V
2.5 V
1.8 V
–8
–6
–4
8
6
4
0.45
0.3
100
CMOS Output Logic
Low Drive
I
OL
3.3 V
2.5 V
1.8 V
CMOS Output Rise/Fall
Time
(20 to 80% V
DD
)
T
R
/T
F
0.1 to 212.5 MHz,
C
L
= 15 pF
0.1 to 212.5 MHz,
C
L
= no load
LVPECL Output
Rise/Fall Time
(20 to 80% VDD)
HCSL Output Rise/Fall
Time (20 to 80% VDD)
LVDS Output Rise/Fall
Time (20 to 80% VDD)
LVPECL Output
Common Mode
LVPECL Output Swing
LVDS Output Common
Mode
T
R
/T
F
T
R
/T
F
T
R
/T
F
V
OC
V
O
V
OC
50
to V
DD
– 2 V,
single-ended
50
to V
DD
– 2 V,
single-ended
100
line-line
V
DD
= 3.3/2.5 V
100
line-line, V
DD
= 1.8 V
100
350
—
0.55
1.13
0.83
0.25
0.35
0.58
48
—
—
V
DD
–
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
470
800
—
0.90
1.33
1.00
0.45
0.42
0.85
52
ps
ps
V
V
PPSE
V
V
V
PPSE
V
V
PPSE
%
LVDS Output Swing
HCSL Output Common
Mode
HCSL Output Swing
Duty Cycle
V
O
V
OC
V
O
DC
Single-ended, 100
differential
termination
50
to
ground
Single-ended
All formats
Rev. 1.3
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
