G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Features :
∗
∗
∗
∗
∗
65,536 words by 16 bits organization.
Fast access time and cycle time.
Dual WE Input.
Low power dissipation.
Read-Modify-Write, RAS -Only Refresh,
Description :
The GLT41316 is a 65,536 x 16 bit high-
performance CMOS dynamic random access
memory. The GLT41316 offers Fast Page
mode ,and has both BYTE WRITE and
WORD WRITE access cycles via two WE
pins. The GLT41316 has symmetric address
and accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 256x16 bits, within a page, with cycle
times as short as 18ns.
The GLT41316 is best suited for
graphics, and DSP applications requiring
high performance memories.
CAS -Before- RAS Refresh, Hidden
Refresh and Test Mode Capability.
∗
256 refresh cycles per 4ms.
∗
Available in 40-pin 400 mil SOJ,and 40/44
pin TSOP (II).
∗
Single 5.0V±10% Power Supply.
∗
All inputs and Outputs are TTL
compatible.
∗
Fast Page Mode operation.
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
AA
)
Min. Fast Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
Max. CAS Access Time (t
CAC
)
30
30 ns
15 ns
18 ns
65 ns
10 ns
35
35 ns
18 ns
21 ns
70 ns
11 ns
40
40 ns
20 ns
23 ns
75 ns
12 ns
45
45 ns
22 ns
25 ns
80 ns
12 ns
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-1-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Pin Configuration :
GLT41316
SOJ Top View
TSOP(Type II)
Top View
Pin Descriptions:
Name
A
0
- A
7
RAS
CAS
UW
LW
OE
DQ
0
- DQ
15
V
CC
V
SS
NC
Function
Address Inputs
Row Address Strobe
Column Address Strobe
Read / Upper Byte Write Enable
Read / Lower Byte Write Enable
Output Enable
Data Inputs / Outputs
+5V Power Supply
Ground
No Connection
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-2-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Absolute Maximum Ratings*
Operating Temperature, T
A
(ambient)
.......................................-0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to V
SS
...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Capacitance*
T
A
=25°C, V
CC
=5V±10%, V
SS
=0V
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
CAS
,
UW
,
LW
,
OE
Max. Unit
5
7
7
pF
pF
pF
Data Input/Output
*Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested
can adversely affect device reliability.
Electrical Specifications
l
l
l
WE means UW and LW .
All voltages are referenced to GND.
After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-3-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Truth Table: GLT41316
Function
Standby
Read: Word
Write: Word(Early Write)
Write: Lower Byte (Early)
Write: Upper Byte (Early)
Read Write
Fast-Page-
Mode Read
Fast-Page-
Mode Write
Fast-Page-
Mode Read-
Write
Hidden
Refresh
2nd Cycle
Read
Write
RAS -Only Refresh
CBR Refresh
L
L→H→L
L→H→L
L
H→L
H→L
L
L
H
L
H→L
H
L
X
X
H→L
H
L
X
X
L→H
L
X
X
X
COL
Data-Out,Data-In
1,2
1
2,3
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
RAS
H
L
L
L
L
L
L
L
L
L
L
CAS
H→X
L
L
L
L
L
H→L
H→L
H→L
H→L
H→L
UW
X
H
L
H
L
H→L
H
LW
X
H
L
L
H
H→L
H
H
OE
X
L
X
X
X
L→H
L
L
X
X
L→H
ADDRESS
High-Z
DQs
Note
s
ROW/COL Data Out
ROW/COL Data-In
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
ROW/COL Data-Out,Data-In
ROW/COL Data-Out
COL
Data-Out
1,2
1
1
2
2
1,2
L
L
H→L
L
L
H→L
ROW/COL Data-In
COL
Data-In
ROW/COL Data-Out,Data-In
ROW/COL Data-Out
ROW/COL Data-In
ROW
High-Z
High-Z
Notes:
1. These READ cycles are always WORD READ cycles .
2. These WRITE cycles may also be BYTE READ cycles (either UW or LW active).
3. EARLY WRITE only.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-4-
G -LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
DC and Operating Characteristics (1-2)
T
A
= 0°C to 70°C, V
CC
=5V±10%, V
SS
=0V, unless otherwise specified.
Sym.
I
LI
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
Operating Current,
Random READ/WRITE
Test Conditions
0V
≤
V
IN
≤
5.5V
(All other pins not under
test=0V)
0V
≤
V
out
≤
5.5V
Output is disabled (Hiz)
t
RC
= t
RC
(min.)
Access
Time
Min.
-10
Typ
Max. Unit Notes
+10
µA
µA
I
LO
I
CC1
-10
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
+10
180
170
160
150
4
mA
1,2
I
CC2
I
CC3
Standby Current,(TTL)
Refresh Current,
RAS-Only
RAS
,
CAS
at V
IH
other inputs
≥V
SS
RAS
cycling,
CAS
at
mA
mA
2
V
IH
t
RC
= t
RC
(min.)
RAS
at V
IL
,
CAS
,
I
CC4
Operating Current,
EDO Page Mode
address cycling: t
PC
=
t
PC
(min.)
RAS
,
CAS
,
I
CC5
Refresh Current,
CAS Before RAS
address cycling:
t
RC
= t
RC
(min.)
RAS
≥V
CC
-0.2V,
CAS
≥V
CC
-0.2V,
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
180
170
160
150
180
170
160
150
180
170
160
150
2
mA
1,2
mA
1
I
CC6
Standby Current, (CMOS)
mA
All other inputs
≥V
SS
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
2.4
I
OL
= 4.2mA
I
OH
= -5mA
2.4
+0.8
V
CC
+1
0.4
V
V
V
V
3
3
Notes:
1.
I
CC
is dependent on output loading when the device output is selected. Specified I
CC(max.)
is measured with the
output open.
2. I
CC
is dependent upon the number of address transitions specified I
CC(max.)
is measured with a maximum of
one transition per address cycle in random Read/Write and Fast Page Mode.
3. Specified V
IL(min.)
is steady state operation. During transitions V
IL(min.)
may undershoot to -1.0V for a period not
to exceed 20ns. All AC parameters are measured with V
IL(min.)
≥V
SS
and V
IH(max.)
≤V
CC
.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-5-
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