Si8660/61/62/63 Data Sheet
Low Power Six-Channel Digital Isolator
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and
5 kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kV
RMS
are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
kV
RMS
.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
RMS
isolation
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
• 2.5 V Operation
• 1.5 mA per channel at 1 Mbps
Applications
•
•
•
•
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
•
•
•
•
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Precise timing (typical)
• 10 ns propagation delay
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 V
RMS
for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 62368-1, 60601-1
(reinforced insulation)
• VDE certification conformity
• VDE 0884-10
• EN60950-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-16 narrow body
• QSOP-16
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Si8660/61/62/63 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs
1,2, 3
Ordering Part Num-
ber (OPN)
QSOP-16 Packages
Si8660BB-B-IU
Si8660EB-B-IU
Si8661BB-B-IU
Si8661EB-B-IU
Si8662BB-B-IU
Si8662EB-B-IU
Si8663BB-B-IU
Si8663EB-B-IU
SOIC-16 Packages
Si8660BA-B-IS1
Si8660BB-B-IS1
Si8660BC-B-IS1
Si8660EC-B-IS1
Si8660BD-B-IS
Si8660ED-B-IS
Si8661BB-B-IS1
Si8661BC-B-IS1
Si8661EC-B-IS1
Si8661BD-B-IS
Si8661ED-B-IS
Si8661BD-B-IS2
6
6
6
6
6
6
5
5
5
5
5
5
0
0
0
0
0
0
1
1
1
1
1
1
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
Low
High
Low
High
Low
Low
High
Low
High
Low
1.0
2.5
3.75
3.75
5.0
5.0
2.5
3.75
3.75
5.0
5.0
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
(8 mm cree-
page)
4
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
6
6
5
5
4
4
3
3
0
0
1
1
2
2
3
3
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
Low
High
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation Rating
(kV)
Temp (°C)
Package
Si8662BB-B-IS1
Si8662BC-B-IS1
Si8662EC-B-IS1
Si8662BD-B-IS
Si8662ED-B-IS
Si8663BB-B-IS1
Si8663BC-B-IS1
Si8663EC-B-IS1
Si8663BD-B-IS
4
4
4
4
4
3
3
3
3
2
2
2
2
2
3
3
3
3
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
High
Low
Low
High
Low
2.5
3.75
3.75
5.0
5.0
2.5
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
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Rev. 1.7 | 2
Si8660/61/62/63 Data Sheet
Ordering Guide
Ordering Part Num-
ber (OPN)
Si8663ED-B-IS
Number of
Inputs
VDD1 Side
3
Number of
Inputs
VDD2 Side
3
Max Data
Rate
(Mbps)
150
Default
Output
State
High
Isolation Rating
(kV)
5.0
Temp (°C)
Package
–40 to 125 °C
WB SOIC-16
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The package designated IS2 has a design that eliminates tie bars, thus allowing for extra creepage distance while maintaining
standard WB SOIC-16 package dimensions and land pattern.
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Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Theory of Operation .
2.2 Eye Diagram .
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. 5
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3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Device Startup
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. 7
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3.2 Undervoltage Lockout .
3.3 Layout Recommendations. .
3.3.1 Supply Bypass . . .
3.3.2 Output Pin Termination.
3.4 Fail-Safe Operating Mode .
.
3.5 Typical Performance Characteristics .
4. Electrical Specifications
5. Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . 28
30
6. Package Outline (16-Pin Wide Body SOIC)
7. Land Pattern (16-Pin Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . .
8. Package Outline (16-Pin Narrow Body SOIC)
. . . . . . . . . . . . . . . . . . 31
9. Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . 33
10. Package Outline (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . 34
11. Land Pattern (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 36
. . . . . . . . . . . . . . . . . . . . 37
. . . . . . . . . . . . . . . . . . .38
12. Top Marking (16-Pin Wide Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
14. Top Marking (16-Pin QSOP)
15. Document Change List
. . . . . . . . . . . . . . . . . . . . . . . . 39
. . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Si8660/61/62/63 Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si866x channel is shown in the figure below.
Transmitter
RF
OSCILLATOR
Receiver
A
MODULATOR
Semiconductor-
Based Isolation
Barrier
DEMODULATOR
B
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.2. Modulation Scheme
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