1CY7C245A
CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
— 330 mW (commercial) for -25 ns
•
•
•
•
•
•
•
•
•
— 660 mW (military)
Programmable synchronous or asynchronous output
enable
On-chip edge-triggered registers
Programmable asynchronous register (INIT)
EPROM technology, 100% programmable
Slim, 300-mil, 24-pin plastic or hermetic DIP
5V
±10%
V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram
INIT
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CP
COLUMN
ADDRESS
ADDRESS
DECODER
PROGRAMMABLE
INITIALIZE WORD
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
O
7
O
6
O
5
8-BIT
EDGE-
TRIGGERED
REGISTER
O
4
O
3
O
2
O
1
O
0
PinConfigurations
DIP
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
A
10
INIT
E/E
S
CP
O
7
O
6
O
5
O
4
O
3
E/E
S
CP
D
C
Q
PROGRAMMABLE
MULTIPLEXER
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 282726
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
121314151617
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
V
CC
A8
A9
LCC/PLCC (Opaque only)
Top View
A
10
INIT
E/E
S
CP
NC
O
7
O
6
Selection Guide
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating Standard
Current
7C245A-15
15
10
120
7C245A-18
18
12
120
120
7C245A-25
25
12
90
120
7C245A-35
35
15
90
120
Unit
ns
ns
mA
mA
Commercial
Military
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 27, 2002
CY7C245A
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................−65
°
C to +150
°
C
Ambient Temperature with
Power Applied..................................................−55
°
C to +125
°
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
.................................................−3.0V
to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm
2
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Military
[2]
Ambient
Temperature
0
°
C to +70
°
C
−55
°
C to +125
°
C
V
CC
5V
±10%
5V
±10%
Electrical Characteristics
Over the Operating Range
[3,4]
7C245A-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
V
CD
I
OZ
I
OS
I
CC
V
PP
I
PP
V
IHP
V
ILP
]
7C245A-18
Min.
2.4
Max.
7C245A-25
7C245A-35
7C245A-45
Min.
2.4
Max.
Unit
V
0.4
2.0
V
CC
0.8
−10
+10
V
V
V
µA
Description
Test Conditions
Min.
2.4
Max.
Output HIGH Voltage V
CC
= Min., I
OH
=
−4.0
mA
V
IN
= V
IH
or V
IL
Output LOW Voltage
Input HIGH Level
Input LOW Level
V
CC
= Min., I
OL
= 16 mA
V
IN
= V
IH
or V
IL
Guaranteed Input Logical
HIGH Voltage for All Inputs
Guaranteed Input Logical
LOW Voltage for All Inputs
0.4
2.0
V
CC
0.8
−10
+10
Note 4
−10
2.0
0.4
V
CC
0.8
+10
Input Leakage Current GND < V
IN
< V
CC
Input Clamp Diode
Voltage
Output Leakage
Current
Output Short
Circuit Current
GND < V
O
< V
CC
Output Disabled
[5]
V
CC
= Max.,
V
OUT
= 0.0V
[6]
Com’l
Mil
−10
−20
+10
−90
120
−10
−20
+10
−90
120
120
−10
−20
+10
−90
90
120
µA
mA
mA
V
mA
V
Power Supply Current V
CC
= Max.,
I
OUT
= 0 mA
Programming Supply
Voltage
Programming Supply
Current
Input HIGH
Programming Voltage
Input LOW
Programming Voltage
12
13
50
12
13
50
12
13
50
3.0
0.4
3.0
0.4
3.0
0.4
V
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04007 Rev. *B
Page 2 of 11
CY7C245A
AC Test Loads and Waveforms
[3, 4]
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
167Ω
R1 250Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
167Ω
R1 250Ω
3.0V
GND
≤
5 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤
5 ns
(a) Normal Load
(b) High Z Load
Equivalent to: TH ÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
Switching Characteristics
Over Operating Range
[3, 4]
7C245A-15
Parameter
t
SA
t
HA
t
CO
t
PWC
t
SES
t
HES
t
DI
t
RI
t
PWI
t
COS
t
HZC
t
DOE
t
HZE
Description
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
E
S
Set-Up to Clock HIGH
E
S
Hold from Clock HIGH
Delay from INIT to Valid Output
INIT Recovery to Clock HIGH
INIT Pulse Width
Valid Output from Clock HIGH
[7]
Inactive Output from Clock
HIGH
[7]
Valid Output from E LOW
[8]
Inactive Output from E HIGH
[8]
10
10
15
15
12
15
10
10
5
15
12
12
15
15
15
15
Min.
15
0
10
12
10
5
20
15
15
15
15
15
15
7C245A-18
Max.
18
0
12
15
12
5
20
20
20
20
20
20
20
7C245A-35
Min.
25
0
12
20
15
5
20
20
25
30
30
30
30
Max.
7C245A-25
Min.
35
0
15
20
15
5
35
Max.
7C245A-35
Min.
45
0
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max. Min.
Notes:
7. Applies only when the synchronous (E
S
) function is used.
8. Applies only when the asynchronous (E) function is used.
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (E
S
) or
asynchronous (E) output enable and asynchronous initialization
(INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (E
S
or E). If the
synchronous enable (E
S
) has been programmed, the register will be
in the set condition causing the outputs (O
0
–O
7
) to be in the OFF or
high-impedance state. If the asynchronous enable (E) is being used,
the outputs will come up in the OFF or high-impedance state only if
the enable (E) input is at a HIGH logic level. Data is read by applying
the memory location to the address inputs (A
0
–A
10
) and a logic LOW
Document #: 38-04007 Rev. *B
to the enable input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up time.
At the next LOW-to-HIGH transition of the clock (CP), data is trans-
ferred to the slave flip-flops, which drive the output buffers, and the
accessed data will appear at the outputs (O
0
–O
7
).
If the asynchronous enable (E) is being used, the outputs may be
disabled at any time by switching the enable to a logic HIGH, and may
be returned to the active state by switching the enable to a logic LOW.
If the synchronous enable (E
S
) is being used, the outputs will go
to the OFF or high-impedance state upon the next positive clock edge
after the synchronous enable input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent
positive clock edge will return the output to the active state. Following
a positive clock edge, the address and synchronous enable inputs
are free to change since no change in the output will occur until the
next LOW-to-HIGH transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the next
location while previously addressed data remains stable on
the outputs.
Page 3 of 11
CY7C245A
Operating Modes
(Continued)
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophisticated
functions such as a built-in “jump start” address. When activated, the
initialize control input causes the contents of a user-programmed
2049th 8-bit word to be loaded into the on-chip register. Each bit is
programmable and the initialize function can be used to load any
desired combination of 1s and 0s into the register. In the unpro-
grammed state, activating INIT will generate a register CLEAR (all
outputs LOW). If all the bits of the initialize word are programmed,
activating INIT performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of the
programmed initialize word into the master and slave flip-flops of the
register, independent of all other inputs, including the clock (CP). The
initialize data will appear at the device outputs after the outputs are
enabled by bringing the asynchronous enable (E) LOW.
Switching Waveforms
[4]
t
HA
A
0
−
A
10
t
SES
E
S
t
SES
t
HES
t
HES
t
SES
t
HES
t
SA
t
HA
CP
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
O
0
−
O
7
t
CO
t
HZC
t
COS
t
CO
t
HZE
E
t
DI
INIT
t
PWI
t
RI
t
DOE
C245A-7
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm
2
power rating the exposure time
would be approximately 35 minutes. The 7C245A needs to be within
1 inch of the lamp during erasure. Permanent damage may result if
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm
2
is the recommended maximum
dosage.
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Bit Map Data
Programmer Address
Decimal
Hex
0
0
.
.
.
.
.
.
2047
7FF
2048
800
2049
801
Control Byte
00 ............ Asynchronous output enable (default state)
01 .....................................Synchronous output enable
RAM Data
Contents
Data
.
.
.
Data
Init Byte
Control Byte
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
Document #: 38-04007 Rev. *B
Page 4 of 11
CY7C245A
Table 1. Mode Selection
Pin Function
[9]
Read or Output Disable
Mode
Read
Output Disable
Initialize
Program
Program Verify
Program Inhibit
Intelligent Program
Program Synchronous Enable
Program Initialization Byte
Blank Check Zeros
Note:
9. X = “don’t care” but not to exceed V
CC
+5%.
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
10
–A
4
A
3
A
3
A
3
A
3
A
3
A
3
A
3
A
3
A
3
V
IHP
V
ILP
A
3
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
2
–A
1
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
V
PP
V
PP
A
0
CP
PGM
V
IL
/V
IH
X
X
V
ILP
V
IHP
V
IHP
V
ILP
V
ILP
V
ILP
V
IHP
E, E
S
VFY
V
IL
V
IH
V
IL
V
IHP
V
ILP
V
IHP
V
IHP
V
IHP
V
IHP
V
ILP
INIT
V
PP
V
IH
V
IH
V
IL
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
O
7
–O
0
D
7
–D
0
O
7
–O
0
High Z
Init. Byte
D
7
–D
0
O
7
–O
0
High Z
D
7
–D
0
High Z
D
7
–D
0
Zeros
Other
DIP
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
A
10
V
PP
VFY
PGM
D
7
D
6
D
5
D
4
D
3
LCC/PLCC (Opaque Only)
Top View
A5
A6
A7
NC
VCC
A8
A9
A
4
A
3
A
2
A
1
A
0
NC
D
0
5
6
7
8
9
10
11
4 3 2 1 28 27 26
25
24
23
22
21
20
19
121314151617 18
A
10
V
PP
VFY
PGM
NC
D
7
D
6
D1
D2
GND
NC
D3
D4
D5
Figure 1. Programming Pinouts
Document #: 38-04007 Rev. *B
Page 5 of 11
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