20MHz 16-bit Microcontroller compatible with Industry
Standard’s MCS-96 ISA
- Register to Register Architecture
- 1000 Byte Register RAM
q
Three 8-bit I/O Ports
q
On-board Interrupt Controller
q
Three Pulse-Width Modulated Outputs
q
High Speed I/O
q
UART Serial Port
q
Dedicated Baud Rate Generator
q
Software and Hardware Timers
- 16-Bit Watchdog Timer, Four 16-Bit Software Timers
- Three 16-Bit Counter/Timers
q
Error detection and correction for external memory accesses
q
QML Q compliant part
q
Standard Microcircuit Drawing 5962-98583
INTRODUCTION
The UT80C196KD is compatible with industry standard’s
MCS-96 instruction set. The UT80C196KD is supported by
commercial hardware and software development tools.
The UT80C196KD accesses instruction code and data via a
16-bit address and data bus. The 16-bit bus allows the
microcontroller to access 128K bytes of instruction/data
memory. Integrated software and hardware timers, high speed
I/O, pulse width modulation circuitry, and UART make the
UT80C196KD ideal for control type applications. The CPU’s
ALU supports byte and word adds and subtracts, 8 and 16 bit
multiplies, 32/16 and 16/8 bit divides, as well as increment,
decrement, negate, compare, and logical operations. The
UT80C196KD’s interrupt controller prioritizes and vectors 18
interrupt events. Interrupts include normal interrupts and
special interrupts. To reduce power consumption, the
microcontroller supports software invoked idle and power
down modes.
The UT80C196KD is packaged in a 68-lead quad flatpack.
1000 Bytes
RAM
Register File
ALU
Interrupt
Controller
PTS
MicroCode
Engine
Memory
Controller
Queue
Address /Data Bus
Watchdog
Timer
PWM
Serial
Port
HSIO and
Timers
HSI HSO
Alternate
Functions
PORT0
EXTINT
Alternate
Functions
HOLD
HLDA
BREQ
PWM1
PWM2
PORT2
PORT1
ECB0-
ECB5
Figure 1. UT80C196KD Microcontroller
F
C irst
or Pa
e
IP ss
Control
Signals
CPU
1.0 SIGNAL DESCRIPTION
Port 0 (P0.0 - P0.7):
Port 0 is an 8-bit input only port when used
in its default mode. When configured for their alternate function,
five of the bits are bi-directional EDAC check bits as shown in
Table 1.
Port 1 (P1.0 - P1.7):
Port 1 is an 8-bit, quasi-bidirectional, I/O
port. All pins are quasi-bidirectional unless the alternate
function is selected per Table 2. When the pins are configured
for their alternate functions, they act as standard I/O, not quasi-
bidirectional.
Port 2 (P2.0 - P2.7):
Port 2 is an 8-bit, multifunctional, I/O port.
These pins are shared with timer 2 functions, serial data I/O and
PWM0 output, per Table 3.
P1.4
AD0-AD7:
The lower 8-bits of the multiplexed address/data
bus. The pins on this port are bidirectional during the data phase
of the bus cycle.
P1.5
AD8-AD15:
The upper 8-bits of the multiplexed address/data
bus. The pins on this port are bidirectional during the data phase
of the 16-bit bus cycle. When running in 8-bit bus width, these
pins are non-multiplexed, dedicated upper address bit outputs.
HSI:
Inputs to the High Speed Input Unit. Four HSI pins are
available: HSI.0, HSI.1, HSI.2, and HSI.3. Two of these pins
(HSI.2 and HSI.3) are shared with the HSO Unit. Two of these
pins (HSI.0 and HSI.1) have alternate functions for Timer 2.
HSO:
Outputs from the High Speed Output Unit. Six HSO pins
are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, and
HSO.5. Pins HSO.4 and HSO.5 are shared with pins HSI.2 and
HSI.3 of the HSI Unit respectively.
BREQ
PWM2
Table 2. Port 1 Alternate Functions
Port
Pin
P1.0
P1.1
P1.2
P1.3
Alternate
Name
P1.0
P1.1
P1.2
PWM1
Alternate Function
I/O Pin
I/O Pin
I/O Pin
Setting IOC3.2=1 enables P1.3 as
the Pulse Width Modulator
(PWM1) output pin.
Setting IOC3.3=1 enables P1.4 as
the Pulse Width Modulator
(PWM2) output pin.
Bus Request, output activated
when the bus controller has a
pending external memory cycle.
Bus Hold Acknowledge, output
indicating the release of the bus.
Bus Hold, input requesting control
of the bus.
P1.6
P1.7
HLDA
HOLD
Table 3. Port 2 Alternate Functions
Port
Pin
P2.0
P2.1
P2.2
Alternate
Name
TXD
RXD
EXTINT
Alternate Function
Transmit Serial Data.
Receive Serial Data.
External interrupt. Clearing
IOC1.1 will allow P2.2 to be
used for EXTINT (INT07)
Timer 2 clock input and Serial
port baud rate generator input.
Timer 2 Reset
Pulse Width Modulator
output 0
Controls the direction of the
Timer 2 counter. Logic High
equals count down. Logic low
equals count up.
A rising edge on P2.7 causes
the value of Timer 2 to be
captured into this register, and
generates a Timer 2 Capture
interrupt (INT11).
Table 1. Port 0 Alternate Functions
Port Pin
P0.0-P0.3,
P0.6
P0.4
P0.5
P0.7
EXTINT
Alternate
Name
ECB0-ECB4
Alternate Function
P2.3
P2.4
T2CLK
T2RST
PWM0
T2UP-DN
Error Detection & Correction
Check Bits
Input Port Pins
P2.5
P2.6
Setting IOC1.1=1 will allow P0.7
to be used for EXTINT (INT07)
P2.7
T2CAPTURE
2
1.1 Hardware Interface
1.1.1 Interfacing with External Memory
The UT80C196KD can interface with a variety of external
memory devices. It supports either a fixed 8-bit bus width or a
dynamic 8-bit/16-bit bus width, internal READY control for
slow external memory devices, a bus-hold protocol that enables
external devices to take over the bus, and several bus-control
modes. These features provide a great deal of flexibility when
interfacing with external memory devices.
1.1.1.1 Chip Configuration Register
The Chip Configuration Register (CCR) is used to initialize the
UT80C196KD immediately after reset. The CCR is fetched
from external address 2018H (Chip Configuration Byte) after
removal of the reset signal. The Chip Configuration Byte (CCB)
is read as either an 8-bit or 16-bit word depending on the value
of the BUSWIDTH pin. The composition of the bits in the CCR
are shown in Table 4.
There are 8 configuration bits available in the CCR. However,
bits 7 and 6 are not used by the UT80C196KD. Bits 5 and 4
comprise the READY mode control which define internal limits
for waitstates generated by the READY pin. Bit 3 controls the
definition of the ALE/ADV pin for system memory controls
while bit 2 selects between the different write modes. Bit 1
selects whether the UT80C196KD will use a dynamic 16-bit
bus or whether it will be locked in as an 8-bit bus. Finally, Bit
0 enables the Power Down mode and allows the user to disable
this mode for protection against inadvertent power downs.
1.1.1.2 Bus Width and Memory Configurations
The UT80C196KD external bus can operate as either an 8-bit
or 16-bit multiplexed address/data bus (see figure 2). The value
of bit 1 in the CCR determines the bus operation. A logic low
value on CCR.1 locks the bus controller in 8-bit bus mode. If,
however, CCR.1 is a logic high, then the BUSWIDTH signal is
used to decide the width of the bus. The bus is 16 bits wide when
the BUSWIDTH signal is high, and is 8 bits when the
BUSWIDTH signal is low.
1.1.2 Reset
To reset the UT80C196KD, hold the RESET pin low for at least
16 state times after the power supply is within tolerance and the
oscillator has stabilized. Resets following the power-up reset
may be asserted for at least one state time, and the device will
turn on a pull-down transistor for 16 state times. This enables
the RESET signal to function as the system reset. The reset state
of the external I/O is shown in Table 9, and the register reset
values are shown in Table 8.
1.1.3 Instruction Set
The instruction set for the UT80C196KD is compatible with the
industry standard MCS-96 instruction set used on the
80C196KD.
Table 4. Chip Configuration Register
Bit
7
6
5
4
3
2
1
0
Function
N/A
N/A
IRC1 - Internal READY Mode Control
IRC0 - Internal READY Mode Control
Address Valid Strobe Select (ALE/ADV)
Write Strobe Mode Select (WR and BHE/WRL and WRH)
Dynamic Bus Width Enable
Enable Power Down Mode
Table 5. Memory Map
Memory Description
External Memory
1
Reserved
PTS Vectors
Upper Interrupt Vectors
Reserved
Reserved
Chip Configuration Byte
Reserved
Lower Interrupt Vectors
External Memory
Internal Memory (RAM)
Special Function Registers
Begin
02080H
0205EH
02040H
02030H
02020H
02019H
02018H
02014H
02000H
00400H
0001AH
00000H
End
0FFFFH
0207FH
0205DH
0203FH
0202FH
0201FH
02018H
02017H
02013H
1FFFH
003FFH
00019H
Notes:
1.The first instruction read following reset will be from location 2080h. All other external memory can be used as instruction and/or data memory.
3
Table 6. Interrupt Vector Sources, Locations, and Priorities
Interrupt
Vector
Location
2012h
2010h
203Eh
203Ch
203Ah
2038h
2036h
2034h
2032h
2030h
200Eh
200Ch
PTS
Vector
Location
N/A
N/A
N/A
205Ch
205Ah
2058h
2056h
2054h
2052h
2050h
204Eh
204Ch
Priority
1
(0 is the
Lowest
Priority)
N/A
N/A
15
14
13
12
11
10
9
8
7
6
Number
Interrupt Vector
Source(s)
Special
Special
INT 15
INT 14
INT 13
INT 12
INT 11
INT 10
INT 9
INT 8
INT 7
INT 6
Unimplemented
Opcode
Software Trap
NMI
2
HSI FIFO Full
EXTINT 1
2
Timer 2 Overflow
Timer 2 Capture
2
HSI FIFO 4
Receive
Transmit
EXTINT
2
Serial Port
Unimplemented Opcode
Software Trap
NMI
HSI FIFO Full
Port 2.2
Timer 2 Overflow
Timer 2 Capture
HSI FIFO
Fourth Entry
RI Flag
3
TI Flag
3
Port 2.2 or Port 0.7
RI Flag and
TI Flag
4
Software Timer 0-3
Timer 2 Reset
HSI.0 Pin
Events on HSO.0 thru
HSO.5 Lines
HSI FIFO Full or
HSI Holding Reg.
Loaded
Single Bit Error
Single Bit Error OVF
Double Bit Error
Timer 1 or Timer 2
INT 5
INT 4
INT 3
INT 2
Software Timer
HSI.0
2
High Speed
Outputs
HSI Data Available
200Ah
2008h
2006h
2004h
204Ah
2048h
2046h
2044h
5
4
3
2
INT 1
EDAC Bit Error
2002h
2042h
1
INT 0
Timer Overflow
2000h
2040h
0
All of the previous maskable interrupts can be assigned to the PTS.
Any PTS interrupt has priority over all other maskable interrupts.
4
Notes:
1.
The Unimplemented Opcode and Software Trap interrupts are not prioritized. The Interrupt Controller immediately services these interrupts when they are
asserted. NMI has the highest priority of all prioritized interrupts. Any PTS interrupt has priority over lower priority intterupts, and over all other maskable
interrupts. The standard maskable interrupts are serviced according to their priority number with INT0 has the lowest priority of all interrupts.
2.
These interrupts can be configured to function as independant, external interrupts.
3.
If the Serial interrupt is masked and the Receive and Transmit interrupts are enabled, the RI flag and TI flag generate separate Receive and Transmit inter-
rupts.
4.
If the Receive and Transmit interrupts are masked and the Serial interrupt is enabled, both RI flag and TI flag generate a Serial Port interrupt.
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