WTSC144.xxx
–
Wire Bonding Temperature
Silicon Vertical Capacitor
Rev 3.1
Key features
n
Ultra high stability of capacitance value:
w
Temperature ±1.5% (-55°C to +200°C)
w
Voltage <0.1%/Volts
w
Negligible capacitance loss through ageing
n
Custom sizes, values, shapes, tolerances and
higher voltage
n
Low leakage current down to 100pA
n
Low profile
Thanks to the unique IPDiA Silicon capacitor
technology, most of the problems encountered in
demanding applications can be solved.
The
capacitor
²
Key applications
Any demanding applications,
such as
medical, aerospace, automotive industrial…
n
Full compatible to monolithic ceramic capacitors
n
n
Applicable for standard wire bonding
approach
( ball and wedge)
n
n
n
Decoupling / Filtering / Charge pump
(i.e: Pacemakers / defibrillators)
High reliability applications
Downsizing
The IPDiA technology is the most appropriate
solution for Chip On Board, Chip On Foil, Chip On
Glass, Chip On Ceramic, flip chip and embedded
integration
capability
(up
to
than
applications, when designers are looking at
utmost decoupling behaviours.
This Silicon based technology is ROHS compliant
and compatible with lead free reflow soldering
250nF/mm )
allows
smaller
footprint
ceramic alternative to answer strong volumes
constraints.
This
technology
provides
industry
leading
process.
performances relative to the
capacitor stability
over the full -55°C/+200°C temperature with a
TC<1.5%.
WTSC
are dedicated to applications where
reliability
up to
200°C
is the main parameter.
WTSC144.xxx
Electrical specification
Capacitance value
10
1pF
15
22
33
47
68
10pF:
935.144.522.210
15pF:
935.144.528.210 935.144.528.215
100pF:
150pF:
22pF:
33pF:
47pF:
68pF:
935.144.528.222 935.144.528.233 935.144.528.247 935.144.528.268
220pF:
330pF:
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680pF:
935.144.521.368
10pF
935.144.522.310 935.144.522.315 935.144.528.322 935.144.528.333
935.144.521.310 935.144.528.315
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22nF:
935.144.827.522
935.144.624.522
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0.1nF
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Parameters
Capacitance range
Capacitance tolerances
Operating temperature range
Storage temperatures
Temperature coefficient
Breakdown Voltage (BV)
Capacitance variation versus
RVDC
Equivalent Serial Inductor (ESL)
Equivalent Serial Resistor (ESR)
Insulation resistance
Aging
Reliability
Capacitor height
(*) Other values on request
Value
10pF to 22nF
±15%
(*)
-55 to 200 °C
(*)
- 70 to 215 °C
±1.5%, from -55 to +200°C
90, 50, 30VDC
(*)
0.1 % /V (from 0 V to RVDC)
Max 100 pH
Max 100 mW
100G
W
@16V,25°C
20G
W
@16V,200°C
Negligible, < 0.001% / 1000h
FIT<0.017 parts / billions hours,
RVDC, from -55 to +200°C
Max 250µm
(*)
Capacitance change (%)
Capacitance change (%)
Capacitance change (%)
-20
-30
-40
X7R
X7R
Capacitance change (%)
Unit
1nF
10nF:
935.144.620.510
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10nF
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Temperature coefficient
PICS vs. MLCC capacitors
20
10
0
-10
Z5U
C0G
PICS
10
DC Voltage stability
MLCC capacitors vs. PICS
PICS
0
PICS
-10
-20
-30
X7R
-40
-50
-60
-70
-80
Y5V
C0G
C0G
X8R
X8R
Y5V
-50
-60
-70
Z5U
Z5U
Temperature (°C)
Y5V
Y5V
-80
-50
0
50
Temperature (°C)
Temperature (°C)
100
150
200
-90
-100
0
1
2
3
Bias voltage (V)
4
5
6
7
Fig.1 Capacitance change versus temperature
variation compared to alternative technologies
Part Number
935.144
B.2
Breakdown
Voltage
Fig.2 Capacitance change versus voltage
variation compared to alternative
technologies
S.
Size
0 = 0303 7 = 0402
1 = 0202 8 = 0201
2 = 0101
3 = 0404
4 = 0504
5= 0302
6 = 0503
U
Unit
0 = 10 f
1 = 0.1 p
2=1p
3 = 10 p
4 = 0.1 n
xx
i.e: 10nF/0303 case (WTSC type)
à
935.144.620.510
8= 30V
6= 50V
5= 90V
52=90V
5=1n
6 = 10 n
7 = 0.1 µ
8=1µ
9 = 10 µ
Value (E6)
10
15
22
33
47
68
Termination & Outline
Termination
Outer electrodes in 3um Aluminum (Al/Si/Cu:
98.96%/1%/0;04%) or Nickel Gold electroless
(Au:0.1um/Ni:5um),
other
finishings
are
available on request such as thin fine Gold
Titanium (Au: 2um) or Copper (Cu:5um).
Applicable for standard wire bonding approach
(ball and wedge).
Typical dimensions, all dimensions in mm.
Typ.
Package outline
0101
0.26
A
Pads opening
±0.02
Comp.
size Min pitch
0.26
B
±0.02
L
Comp. size
Back
W
metalization
A
area
L
Comp. size
W
L
Comp. size
W
0201
0202
0.463
COB
0.463
±0.05
60µm
±0.05
0.26
100µm
0.463
±0.02
±0.05
0.05
0.05
C
0.05
0.05
0.05
B
0303
0.80
±0.05
0.80
±0.05
Top
metalization
area
0402
1.02
±0.05
0.463
±0.05
0404
1.02
±0.05
1.02
±0.05
0504
1.37
±0.05
1.02
±0.05
e
0.05
d
Packaging
Tape and reel, tray, waffle pack or wafer delivery.
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 28
th
February 2014
Document identifier : CL 431 111 615 148
IPD Capacitor Assembly Set Up
Rev 1.0
Application Note
Outline
Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging
with the following features:
Package dedicated to solve tombstoning effect of small SMD package;
Package compatible with SMD assembly;
Package without underfilling step;
Interconnect available with various optional finishing for specific assembly.
Assembly consideration
Standard pick & place equipment dedicated to WLCSP down to 400µm pitch.
Solder paste type 3 in most cases of EIA size.
Reflow has to be done with standard lead-free profile (for SAC alloys) or
according to JEDEC recommendations J-STD 020D-01.
Lead
Leadfree
Tp: 235 °C
T
L: 183 °C
Ts min: 100 °C
Ts max: 150 °C
t
L
: 60-150 s
Tp: 260 °C
T
L:
217 °C
Ts min: 150 °C
Ts max: 200 °C
t
L
: 60-150 s
Process recommendation
After soldering, no solder paste should touch the side of the capacitor die as that might results in
leakage currents due to remaining flux.
In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder
flux must be cleaned after reflow soldering step.
Notes: for a proper flux cleaning process, “rosin” flux type (R) or “water soluble” flux type (WS) is
recommended for the solder printing material. “No clean” flux (NC) solder paste is not recommended.
In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be
appropriate and the solder volume must be controlled:
- using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a
proper printing process.
- Mirroring pads would be the best recommendation
Application Note
Pad recommendation
The capacitor is compatible with generic requirements for flip chip design (IPC7094).
Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, …).
Die size and land pattern dimensions is set up according to following range :
EIA size
Dimension max(X1 x X2) mm
Typical . die thickness X3 (mm)
Typical pad size* (mm)
Typical pad separation (X4
mm)
0201
0.86x0.66
0402
1.26x0.76
0603
1.86x1.16
0805
2.26x1.46
1206
3.46x1.86
1812
4.76x3.66
0.1 or 0.4
0.15x0.40
0.3
0.30x0.50
0.4
0.40x0.90
0.8
0.50x1.20
1
0.60x1.60
2
0.90x3.40
2.7
X3
X2
X1
Top side
silicon
Typ.UBM thickness
3 to 5 µm
X4
After soldering, no solder paste should touch the side of the capacitor die as that might result in
leakage currents due to remaining flux.
Rev 1.0
2 of 3
Application Note
Manual Handling Considerations
These capacitors are designed to be mounted with a standard SMT line, using solder printing step,
pick and place machine and a final reflow soldering step. In case of manual handling and mounting
conditions, please follow below recommendations:
Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is
recommended).
Use of organic tip instead of metal tip for the nozzle.
Minimize temperature shocks (Substrate pre-heating is recommended).
No wire bonding on 0402 47nF, 0402 100nF, 1206 1 F and 1812 3,3µF
Process steps:
On substrate, form the solder meniscus on each land pattern targeting 100 µm
height after reflow (screen printing, dispensing solder paste or by wire soldering).
Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible
using a vacuum nozzle and organic tip.
Temporary place the capacitor on land pattern assuming the solder paste (Flux)
will stick and maintain the capacitor.
Reflow the assembly module with a dedicated thermal profile (see reflow
recommendation profile).
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 20
th
April 2012
Document identifier:
电源技术
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