NBXSPA022
2.5 V / 3.3 V, 187.5 MHz
LVDS Clock Oscillator
The NBXSPA022 single frequency crystal oscillator (XO) is
designed to meet today’s requirements for 2.5 V and 3.3 V LVDS
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide 187.5 MHz,
ultra low jitter and phase noise LVDS differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
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MARKING DIAGRAM
NBXSPA022
187.5
AAWLYYWWG
•
•
•
•
•
•
•
LVDS Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise
−
0.5 ps (12 kHz
−
20 MHz)
Output Frequency
−
187.5 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range: 2.5 V
±5%
Operating Range:
3.3 V
±10%
•
Total Frequency Stability
−
$50
ppm
•
This is a Pb−Free Device
Applications
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXSPA022
187.5
AA
WL
YY
WW
G or
G
= NBXSPA022 (±50 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NBXSPA022LN1TAG
NBXSPA022LNHTAG
Package
CLCC−6
(Pb−Free)
CLCC−6
(Pb−Free)
Shipping
†
1000/
Tape & Reel
100/
Tape & Reel
•
12 Gb/s Ethernet Clock
V
DD
6
CLK CLK
5 4
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1
OE
2
NC
3
GND
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 1
1
Publication Order Number:
NBXSPA022/D
NBXSPA022
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
OE
NC
I/O
LVTTL/LVCMOS
Control Input
N/A
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
No Connect
Ground 0 V
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Á Á
GND
CLK
CLK
V
DD
Power Supply
LVDS Output
LVDS Output
Non−Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Positive power supply voltage. Voltage should not exceed 2.5 V
±5%
or 3.3 V
±10%.
Power Supply
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
V
DD
I
out
T
A
T
stg
T
sol
Parameter
Positive Power Supply
LVDS Output Current
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 5
Condition 1
GND = 0 V
Continuous
Surge
Condition 2
Rating
4.6
25
50
−40
to +85
−55
to +120
260
Units
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXSPA022
Table 5. DC CHARACTERISTICS
(V
DD
= 2.5 V
±
5% or V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 2)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
DV
OD
Characteristic
Power Supply Current
OE Input HIGH Voltage
OE Input LOW Voltage
Input HIGH Current
Input LOW Current
Change in Magnitude of V
OD
for
Complementary Output States
(Note 3)
Offset Voltage
Change in Magnitude of V
OS
for
Complementary Output States
(Note 3)
Output HIGH Voltage
Output LOW Voltage
Differential Output Voltage
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
900
250
2000
GND
−
300
−100
−100
0
1
Conditions
Min.
Typ.
85
Max.
105
V
DD
800
+100
+100
25
Units
mA
mV
mV
mA
mA
mV
V
OS
DV
OS
1125
0
1
1375
25
mV
mV
V
OH
V
OL
V
OD
1425
1075
1600
mV
mV
450
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
3. Parameter guaranteed by design verification not tested in production.
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3
NBXSPA022
Table 6. AC CHARACTERISTICS
(V
DD
= 2.5 V
±
5% or V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 4)
Symbol
f
CLKOUT
Df
F
NOISE
Characteristic
Output Clock Frequency
Frequency Stability
−
NBXSPA022
Phase−Noise Performance
f
CLKout
= 187.5 MHz
(See Figure 3)
(Note 5)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
t
jit
(F)
t
jitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
Period, Peak−to−Peak
t
OE/OD
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Start−up Time
Aging
1
st
Year
Every Year After 1
st
48
50
250
250
1
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
−96
−117
−124
−126
−133
−158
0.5
1
7
0.6
5
0.75
8
35
4
20
200
52
400
400
5
3
1
Conditions
Min.
Typ.
187.5
±50
Max.
Units
MHz
ppm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
ps
ps
ps
ns
%
ps
ps
ms
ppm
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
Figure 3. Typical Phase Noise Plot at 187.5 MHz
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NBXSPA022
Table 7. RELIABILITY COMPLIANCE
Parameter
Shock
Mechanical
Mechanical
Mechanical
Mechanical
Mechanical
Standard
Method
MIL−STD−833, Method 2002, Condition B
MIL−STD−833, Method 2003
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Á
Á
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Á
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Á
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Solderability
Vibration
MIL−STD−833, Method 2007, Condition A
MIL−STD−202, Method 215
Solvent Resistance
Resistance to Soldering Heat
Thermal Shock
MIL−STD−203, Method 210, Condition I or J
MIL−STD−833, Method 1001, Condition A
MIL−STD−833, Method 1004
Environment
Environment
Moisture Resistance
NBXSPA022
CLK
Driver
Device
CLK
Z
o
= 50
W
Z
o
= 50
W
100
W
D
D
Receiver
Device
Figure 4. Typical Termination for Output Driver and Device Evaluation
Temperature (°C)
260
217
temp. 260°C
20
−
40 sec. max.
peak
3°C/sec. max.
ramp−up
6°C/sec. max.
cooling
175
150
pre−heat
reflow
60180 sec.
60150 sec.
Time
Figure 5. Recommended Reflow Soldering Profile
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