19-3535; Rev 1; 5/07
MAX19541/MAX19542 Evaluation Kits
General Description
The MAX19541/MAX19542 evaluation kits (EV kits) are
fully assembled and tested printed-circuit boards
(PCBs) that contain all the components necessary to
evaluate the performance of the MAX19541 (125Msps)
and MAX19541/MAX19542 (170Msps) 12-bit analog-to-
digital converters (ADCs). The MAX19541/MAX19542
accept differential analog inputs; however, the EV kits
generate this signal from a user-provided, single-ended
signal source. The digital outputs produced by the ADC
are CMOS compatible and can be easily captured with
a user-provided, high-speed logic analyzer or data-
acquisition system. The EV kits operate from 1.8V and
3.3V power supplies and include circuitry that generates
a clock signal from a user-provided AC signal.
Features
♦
Up to 170Msps Sampling Rate Using the MAX19542
♦
Up to 125Msps Sampling Rate Using the MAX19541
♦
Low-Voltage and Low-Power Operation
♦
Fully Differential Input Signal Configuration
♦
On-Board Output Buffers
♦
Fully Assembled and Tested
Evaluate: MAX19541/MAX19542
Ordering Information
PART
MAX19541EVKIT+
MAX19542EVKIT+
TEMP RANGE
0°C to +70°C*
0°C to +70°C*
IC PACKAGE
68 QFN-EP**
68 QFN-EP**
+Denotes
a lead-free and RoHS-compliant EV kit.
*This
limited temperature range applies to the EV kit PCB only.
The MAX19541/MAX19542 IC temperature range is -40°C to
+85°C.
**EP
= Exposed paddle.
Component List
DESIGNATION
C1, C2, C3,
C5–C27
C4
QTY
26
DESCRIPTION
0.1µF ±10%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104K
Not installed, ceramic capacitor
(0402)
0.22µF ±10%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J224K
47µF ±10%, 10V tantalum
capacitors (C case)
AVX TAJC476K010
10µF ±20%, 6.3V X5R ceramic
capacitors (0805)
TDK C2012X5R0J106M
1.0µF ±10%, 10V X5R ceramic
capacitors (0603)
TDK C1608X5R1A105K
0.01µF ±20%, 25V X7R ceramic
capacitor (0402)
TDK C1005X7R1E103M
Not installed, shorted by PC trace
(0603)
INP, CLK,
RESET
INN
J1, J2
JU1–JU6, JU8
JU7
R1, R2, R11,
R12, R14,
R15, R22
R3–R7
R8, R9
R10, R13
R16, R17
R18, R19
R20
C43
1
R21
R23–R26
3
0
2
7
1
0
5
2
2
2
2
1
1
0
SMA PC board vertical-mount
connectors
Not installed, vertical-mount SMA
connector
Dual-row 40-pin headers
3-pin headers
Dual-row 8-pin header
Not installed, resistors (0603)
49.9Ω ±1% resistors (0603)
510Ω ±5% resistors (0603)
0Ω resistors (0603)
24.9Ω ±0.1% resistors (0603)
IRC PFC-W0603RLF-02-24R9-B
Panasonic ERA3HB24R9V
24.9Ω ±1% resistors (0603)
100kΩ, 12-turn, 1/4in
potentiometer
13kΩ ±1% resistor (0603)
Not installed, shorted by PC
trace (0603)
0
C28, C29, C30
3
C31–C34
4
C35–C38
4
C39–C42
4
C44, C45
0
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX19541/MAX19542 Evaluation Kits
Evaluate: MAX19541/MAX19542
Component List (continued)
DESIGNATION
RA1–RA4
RA5–RA8
T1, T2
TP1, TP2, TP3
U1
QTY
4
4
2
3
1
DESCRIPTION
100Ω ±5% resistor arrays (1206)
Panasonic EXB-2HV-101J
22Ω ±5% resistor arrays (1206)
Panasonic EXB-2HV-220J
1:1 800MHz RF transformers
Mini-Circuits ADT1-1WT+
Test points (black)
See the
EV Kit-Specific
Component List
3.3V ECL differential receiver
(8-pin SO)
ON Semiconductor
MC100LVEL16DG
—
1
U5
1
DESIGNATION
QTY
DESCRIPTION
Low-voltage, 16-bit flip-flops
(48-pin TSSOP)
Pericom PI74ALVTC16374AE
Dual two-input exclusive-OR gate
(8-pin VSSOP)
TI SN74AUC2G86DCURE4
PCB: MAX19541/MAX19542
Evaluation Kit+
U3, U4
2
EV Kit-Specific Component list
EV KIT PART
NUMBER
MAX19541EVKIT+
U1
MAX19542EVKIT+
MAX19542EGK+
(68-pin QFN with EP,
10mm x 10mm x 0.9mm)
REFERENCE
DESIGNATOR
DESCRIPTION
MAX19541EGK+
(68-pin QFN with EP,
10mm x 10mm x 0.9mm)
U2
1
Component Suppliers
SUPPLIER
AVX Corp.
IRC, Inc.
Panasonic Corp.
PHONE
843-946-0238
361-992-7900
714-373-7183
FAX
843-626-3123
361-992-3377
714-373-7939
WEBSITE
www.avxcorp.com
www.irctt.com
www.panasonic.com
TDK Corp.
847-803-6100
847-390-4405
www.component.tdk.com
Note:
Indicate that you are using the MAX19541/MAX19542 when contacting these component suppliers.
Quick Start
Recommended Equipment
• DC power supplies:
Analog
Clock
Buffers
Digital
(AVCC)
(CVCC)
(BVCC)
(OVCC)
1.8V, 1A
3.3V, 500mA
1.8V, 500mA
1.8V, 1A
• Logic analyzer or data-acquisition system (e.g., HP
16500C with high-speed state card such as the HP
16517A
• Digital voltmeter
Procedure
The MAX19541/MAX19542 EV kits are fully assembled
and tested surface-mount boards. Follow the steps below
for board operation.
Caution: Do not turn on power
supplies or enable signal generators until all connec-
tions are completed:
1) Verify that shunts are installed in the following
locations:
a) JU1 (1-2)—Divide-by-two disabled
b) JU2 (2-3)—Parallel mode selected
• Signal generator with low phase noise for clock input
signal (e.g., HP 8662A, HP 8644B)
• Signal generator for analog input signal (e.g., HP
8662A, HP 8644B)
2
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
c) JU3 (2-3)—Demux parallel mode selected if
JU2 is pulled high
d) JU4 (2-3)—Two’s-complement output selected
e) JU5 (1-2)—Noninverted DCLKP selected
f) JU6 (2-3)—Noninverted DCLKN selected
g) JU7 (3-4)—Internal reference enabled
2) Connect the clock signal generator to the SMA
connector labeled CLK.
3) Connect the analog input signal generator to the
SMA connector labeled INP.
4) Connect the logic analyzer’s high-speed state card
probe connectors to header J1 (CMOS-compatible
signals); see
Table
5 for header connections.
5) Connect a 1.8V, 1A power supply to AVCC.
Connect the ground terminal of this supply to the
GND pad closest to the AVCC pad.
6) Connect a 3.3V, 500mA power supply to CVCC.
Connect the ground terminal of this supply to the
GND pad closest to the CVCC pad.
7) Connect a 1.8V, 500mA power supply to BVCC.
Connect the ground terminal of this supply to the
GND pad closest to the BVCC pad.
8) Connect a 1.8V, 1A power supply to OVCC.
Connect the ground terminal of this supply to the
GND pad closest to the OVCC pad.
9) Turn on all the power supplies.
10) Enable the signal generators. Set the clock signal
generator to output a 170MHz signal, with a 2.4V
P-P
amplitude. Set the analog input signal generato to
output the desired frequency with an amplitude
≤2V
P-P
. For coherent sampling, the signal genera-
tors should be synchronized.
11) Enable the logic analyzer.
12) Collect data using the logic analyzer.
load signals that can be captured by a wide variety of
logic analyzers. The buffered CMOS outputs can be
accessed at headers J1 and J2.
Each EV kit is designed as a four-layer PCB to optimize
the performance of the MAX19541/MAX19542. Separate
analog, digital, clock, and buffer power planes minimize
noise coupling between analog and digital signals; 50Ω
coplanar transmission lines are used for analog and
clock inputs. The trace lengths of the 50Ω CMOS lines
are matched to within a few thousandths of an inch to
minimize layout-dependent delays.
Evaluate: MAX19541/MAX19542
Power Supplies
The MAX19541/MAX19542 EV kits require separate
analog, digital, clock, and buffer power supplies for
best performance. Two separated 1.8V power supplies
are used to power the analog and digital portions of the
MAX19541/MAX19542. The on-board clock circuitry is
powered by another 3.3V power supply, and a 1.8V
power supply is used to power the output buffers (U3
and U4) on the EV kits.
Clock
The MAX19541/MAX19542 require a differential clock
signal. However, if only a single-ended clock signal
source is available, the EV kit’s on-board level transla-
tor helps to convert a single-ended clock to the
required differential signal. An on-board clock-shaping
circuit generates a differential clock signal from an AC-
coupled sine-wave signal applied to the clock input
SMA connector CLK. The input signal amplitude should
not exceed 2.6V
P-P
. The frequency of the clock signal
should not exceed 170MHz. The frequency of the sinu-
soidal input clock signal determines the sampling fre-
quency (f
CLK
) of the ADC. A differential line receiver
(U2) processes the input signal to generate the
required clock signal.
Clock Divider
The MAX19541/MAX19542 feature an internal divide-
by-two clock divider. Use jumper JU1 to enable/disable
this feature. See
Table
1 for shunt positions.
Detailed Description
The MAX19541/MAX19542 EV kits are fully assembled
and tested PCBs that contain all the components nec-
essary to evaluate the performance of the
MAX19541/MAX19542. The MAX19541/MAX19542 can
be evaluated with a maximum clock frequency (f
CLK
) of
170MHz.
The MAX19541/MAX19542 accept differential inputs.
Applications that only have a single-ended signal source
available can use the on-board transformer (T2) to con-
vert a single-ended signal to a differential signal.
Output buffers (U3 and U4) buffer the digital output sig-
nals of the MAX19541/MAX19542 to higher capacitive
Table
1. Clock-Divider Shunt Settings
(JU1)
SHUNT
POSITION
1-2*
2-3
MAX19541/MAX19542
CLKDIV PIN
Connected to AVCC
Connected to GND
DESCRIPTION
Clock signal
divided by 1
Clock signal
divided by 2
*Default
position.
3
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
Evaluate: MAX19541/MAX19542
Input Signal
The MAX19541/MAX19542 accept differential analog
input signals. However, the EV kits only require a sin-
gle-ended analog input signal with an amplitude of less
than 2V
P-P
provided by the user. An on-board trans-
former then takes the single-ended analog input and
generates a differential analog signal, which is applied
to the ADC’s differential input pins.
Optional Input Transformer
The MAX19541/MAX19542 EV kits use a second trans-
former to enhance THD and SFDR performance at high
input frequencies (>100MHz). This transformer helps to
reduce the increase of even-order harmonics at high
frequencies. To use only the primary transformer, follow
the directions below:
1) Remove R10 and R13.
2) Install a 0.1µF capacitor on C4.
3) Install a 0Ω resistor at R22.
4) Install an SMA connector on INN.
5) Connect the analog signal source to INN instead
of INP.
Reference Voltage
There are two methods to set the full-scale range of the
MAX19541/MAX19542. Both EV kits can be configured
to use the MAX19541/MAX19542’s internal reference, or
a stable, low-noise, external reference can be applied to
the REFIO pad. Jumper JU7 controls which reference
source is used. See
Table
2 for shunt settings.
Output Mode
The MAX19541/MAX19541/MAX19542 feature three
modes of operation: parallel mode, demux parallel
mode, and demux interleaved mode. In each mode of
operation, the digital data is output in a different format
and is controlled by the ADC’s DEMUX and ITL pins.
The EV kits incorporate jumpers JU2 and JU3 to control
the DEMUX and ITL pins, respectively. See
Table
3 for
shunt settings.
Table
2. Reference Shunt Settings (JU7)
SHUNT
POSITION
1-2
3-4*
5-6
7-8
DESCRIPTION
Internal Reference Disabled. Apply an
external reference voltage to the REFIO pad.
Internal Reference Enabled. REFIO is the
output of the internal reference.
Increases FSR through trim potentiometer
R20.
Decreases FSR through trim potentiometer
R20.
*Default
position.
Table
3. Output-Mode Shunt Settings (JU2 and JU3)
JU2 SHUNT
POSITION
2-3
1-2
1-2
DEMUX PIN
Connected to GND
Connected to AV
CC
Connected to AV
CC
JU3 SHUNT
POSITION
—
2-3
1-2
ITL PIN
—
Connected to GND
Connected to AV
CC
OUTPUT MODE
Parallel mode
Demux parallel mode
Demux interleaved
mode
OUTPUT PORT
Port A
Ports A and B
Ports A and B
4
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
Output Format
The digital output coding can be chosen to be either in
two’s complement or straight offset-binary format by
configuring jumper JU4. See
Table
4 for shunt settings.
Output Bit Locations
The buffered digital outputs of the ADC are connected
to two 40-pin headers (J1 and J2). PCB trace lengths
are matched to minimize output skew and improve per-
formance of the device. The buffers are able to drive
large capacitive loads, which may be present at the
logic analyzer connection. See
Table
5 for headers J1
and J2 bit locations.
Evaluate: MAX19541/MAX19542
Table
4. Output-Format Shunt Settings (JU4)
SHUNT POSITION
1-2
2-3*
T/B
PIN
Connected to AV
CC
Connected to GND
DESCRIPTION
Digital data appears in straight offset-binary code.
Digital data appears in two’s-complement code.
Table
5. Output Bit Locations (J1 and J2)
PORT A
BIT
ORA
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DCLKP
BUFFERED
OUTPUT
J1-35
J1-31
J1-29
J1-27
J1-25
J1-23
J1-21
J1-19
J1-17
J1-15
J1-13
J1-11
J1-9
J1-3
LABEL NAME
BORA
BDA11
BDA10
BDA9
BDA8
BDA7
BDA6
BDA5
BDA4
BDA3
BDA2
BDA1
BDA0
CLKA
PORT B BIT
ORB
DB11
DB10
DB9
DB9
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DCLKN
BUFFERED
OUTPUT
J2-35
J2-31
J2-29
J2-27
J2-25
J2-23
J2-21
J2-19
J2-17
J2-15
J2-13
J2-11
J2-9
J2-3
LABEL
NAME
BORB
BDB11
BDB10
BDB9
BDB8
BDB7
BDB6
BDB5
BDB4
BDB3
BDB2
BDB1
BDB0
CLKB
Bit 0 (LSB)
Clock output signal
Bits 10–1
DESCRIPTION
Overrange bit
Bit 11 (MSB)
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5
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