Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
FEATURES
•
In accordance with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
MULTIBYTE™ flow-through pin-out architecture
•
Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
•
Direct interface with TTL levels
•
All data inputs have bus hold
•
Output drive capability 50
Ω
transmission lines at 85
°C
•
Current drive
±24
mA at 3.0 V.
DESCRIPTION
The 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCP
AB
or nCP
BA
) regardless of the select inputs (nS
AB
and nS
BA
) or output enable (nOE
AB
and nOE
BA
) control
inputs.
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°C;
t
r
= t
f
= 2.5 ns.
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
propagation delay nA
n
, nB
n
to nB
n
, nA
n
maximum clock frequency
input capacitance
power dissipation capacitance per latch
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
74ALVCH16652
Depending on the select inputs nS
AB
and nS
BA
data can
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOE
AB
and nOE
BA
determine the
operation mode of the transceiver. When nOE
AB
is LOW,
no data transmission from nB
n
to nA
n
is possible and when
nOE
BA
is HIGH, no data transmission from nB
n
to nA
n
is
possible.
When nS
AB
and nS
BA
are in the real-time transfer mode, it
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOE
AB
and
nOE
BA
. In this configuration each output reinforces its
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
TYPICAL
2.6
350
4.0
22
4.0
ns
UNIT
MHz
pF
pF
pF
1999 Nov 23
2
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
FUNCTION TABLE
See note 1.
INPUTS
nOE
AB
L
L
X
H
L
L
L
L
H
H
H
Notes
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH.
nOE
BA
H
H
H
H
X
L
L
L
H
H
L
nCP
AB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
nCP
BA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
nS
AB
X
X
X
L
X
X
X
X
L
H
H
nS
BA
X
X
X
X
X
L
L
H
X
X
H
DATA I/O
74ALVCH16652
FUNCTION
nA
0
to nA
7
input
input
input
nB
0
to nB
7
input
isolation store A and B data
unspecified
(2)
store A, hold B
output
store A in both registers
hold A, store B
store B in both registers
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
stored A data to B bus and
stored B data to A bus
unspecified
(2)
input
output
input
output
input
output
input
output
output
2. The data output functions may be enabled or disabled by various signals at the nOE
AB
and nOE
BA
inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
1999 Nov 23
3
Philips Semiconductors
Product specification
16-bit transceiver/register with dual enable; 3-state
ORDERING INFORMATION
PACKAGE
OUTSIDE NORTH
AMERICA
74ALVCH16652DGG
PINNING
PIN
1 and 28
2 and 27
3 and 26
5, 6, 8, 9, 10, 12, 13 and 14
4, 11, 18, 25, 32, 39, 46 and 53
7, 22, 35, 50
15, 16, 17, 19, 20, 21, 23 and 24
29 and 56
30 and 55
31 and 54
33, 34, 36, 37, 38, 40, 41 and 42
43, 44, 45, 47, 48, 49, 51 and 52
SYMBOL
1OE
AB
, 2OE
AB
1CP
AB
, 2CP
AB
1S
AB
, 2S
AB
1A
0
to 1A
7
GND
V
CC
2A
0
to 2A
7
2OE
BA
, 1OE
BA
2CP
BA
, 1CP
BA
2S
BA
, 1S
BA
2B
0
to 2B
7
1B
7
to 1B
0
NORTH
AMERICA
ACH16652 DGG
TEMPERATURE
RANGE
−40
to +85
°C
PINS
56
PACKAGE
TSSOP
74ALVCH16652
MATERIAL
plastic
CODE
SOT364-1
DESCRIPTION
output enable A-to-B
clock input A-to-B
select input A-to-B
‘1A’ data inputs/outputs
ground (0 V)
positive supply voltage
‘2A’ data inputs/outputs
output enable B-to-A
clock input B-to-A
select input B-to-A
‘2B’ data inputs/outputs
‘1B’ data inputs/outputs
1999 Nov 23
4
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