NJU8725
PRELIMINARY
CLASS D AMPLIFIER FOR DIGITAL AUDIO
!
GENERAL DESCRIPTION
The
NJU8725
is an 800mW-output class D
th
Amplifier featuring 6
∆Σ
modulation. It includes
Digital Attenuator, Mute, and De-emphasis circuits. It
converts Digital source input to PWM signal output
which is output PWM signal converted to analog
signal with simple external LC Filter. The
NJU8725
realizes very high power-efficiency by class D
operation. Therefore, it is suitable for battery-powered
applications and others.
!
PACKAGE OUTLINE
NJU8725V
!
FEATURES
#
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PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
F0/DATA
F1/REQ
F2/SCK
DIN
V
DDR
OUT
RP
V
SSR
OUT
RN
V
DDR
LRCK
BCK
MCK
Stereo BTL Power Amplifier
Sixth-order 32f
S
Over Sampling
∆Σ
& PWM
V
DD
Internal 8f
S
Over Sampling Digital Filter
STBY
Sampling Frequency : 96kHz (Max.)
TEST
De-Emphasis
: 32kHz, 44.1kHz, 48kHz
MUTE
System Clock
: 256f
S
V
DDL
Digital Processing
: Attenuator 107step, LOG Curve
: Mute
OUT
LP
Digital Audio Interface : 16bit, 18bit
V
SSL
2
: I S, LSB Justified, MSB Justified
OUT
LN
Short Circuit Protection
V
DDL
Operating Voltage
: 3.0 to 3.6V
Driving Voltage
: V
DD
to 5.25V
MODE
C-MOS Technology
RST
Package Outline
: SSOP24
V
SS
!
BLOCK DIAGRAM
V
DD
V
SS
RST
MCK
LRCK
BCK
DIN
MUTE
STBY
MODE
F0/DATA
F1/REQ
F2/SCK
Serial
Audio Data
Interface
8f
S
Over Sampling
Digital Filter
32f
S
6
∆Σ
&
PWM
th
Power On
Reset Circuit
Synchronization
Circuit
Short Circuit
Protection
V
DDL
OUT
LP
V
SSL
V
DDL
OUT
LN
V
SSL
V
DDR
OUT
RP
System
Control
V
SSR
V
DDR
OUT
RN
V
SSR
-1-
NJU8725
!
TERMINAL DESCRIPTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SYMBOL
V
DD
STBY
TEST
MUTE
V
DDL
OUT
LP
V
SSL
OUT
LN
V
DDL
MODE
RST
V
SS
MCK
BCK
LRCK
V
DDR
OUT
RN
V
SSR
OUT
RP
V
DDR
DIN
F2/SCK
I/O
−
I
I
I
−
O
−
O
−
I
I
−
I
I
I
−
O
−
O
−
I
I
FUNCTION
Logic Power Supply, V
DD
=3.3V
Standby Control Terminal
Low : Standby ON
High : Standby OFF
Manufacturer Testing Terminal
Normally connect to GND.
Mute Control Terminal
Low : Mute ON
High : Mute OFF
Lch Power Supply, V
DDL
=V
DD
to 5.0V
Lch Positive Output Terminal
Lch Power GND, V
SSL
=0V
Lch Negative Output Terminal
Lch Power Supply, V
DDL
=V
DD
to 5.0V
Control Mode selection Terminal
Low : Parallel Control Mode
High : Serial Control Mode
Reset Terminal
Low : Reset ON
High : Reset OFF
Logic Power GND, V
SS
=0V
Master Clock Input Terminal
256f
S
clock inputs this terminal.
Serial Audio Data Bit Clock Input Terminal
This clock must synchronize with MCK input signal.
L/R Channel Clock Input Terminal
This clock must synchronize with MCK input signal.
Rch Power Supply, V
DDR
=V
DD
to 5.0V
Rch Negative Output Terminal
Rch Power GND, V
SSR
=0V
Rch Positive Output Terminal
Rch Power Supply, V
DDR
=V
DD
to 5.0V
Serial Audio Data Input Terminal
MODE=”Low” : Serial Audio Interface Format Selection Terminal 2
MODE=”High” : Control Register Data Shift Clock Input Terminal
The data is fetched into the control register by rise edge of SCK
signal.
MODE=”Low” : Serial Audio Interface Format Selection Terminal 1
MODE=”High” : Control Register Data Request Input Terminal
MODE=”Low” : Serial Audio Interface Format Selection Terminal 0
MODE=”High” : Control Register Data Input Terminal
23
24
F1/REQ
F0/DATA
I
I
!
INPUT TERMINAL STRUCTURE
V
DD
Input Terminal
V
SS
Inside Circuit
-2-
NJU8725
!
FUNCTIONAL DESCRIPTION
(1) Signal Output
PWM signals of L channel and R output from OUT
LP
/
LN
and OUT
RP
/
RN
terminals respectively. These signals
are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from
V
DDL
, V
DDR
, V
SSL
, and V
SSR
are required high response power supply against voltage fluctuation like as switching
regulator because Output THD is effected by power supply stability.
(2) Master Clock
Master Clock is 256f
S
clock into MCK terminal for the internal circuit operation clock.
(3) Reset
“L” level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This
initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset
signal. This Reset signal initializes the internal function setting registers also. During initialization, the
output-drivers output GND level. The reset equivalent circuit is shown bellow.
RST
Power on Reset
CLK
(About 10kHz)
Internal Reset
D
D
D
D
D
D
D
D
Figure 1. Reset Equivalent Circuit
(4) 8f
S
Over Sampling Digital Filter
8f
S
Over Sampling Digital Filter interpolates
Audio data and decreases aliasing noise.
It realizes Attenuation and De-Emphasis function by serial function control.
(5) 32f
S
6
∆Σ
& PWM
th
32f
S
6
∆Σ
& PWM convert from Audio data of the 8f
S
Over Sampling Digital Filter to the 32f
S
one bit PWM
data.
th
(6) Short Circuit Protection
Short Circuit Protection protects IC with output terminal of high-impedance condition when output terminal is
shorted to GND or other output terminal.
The high-impedance condition is released automatically with master clock input, not released without master
clock input.
-3-
NJU8725
(7) System Control
(7-1) Standby
Standby functions by “L” level input to the STBY terminal. In busy of Standby, conditions of digital audio
format set, attenuation level, de-emphasis, and attenuator operation time are kept and output terminals are
high-impedance.
(7-2) Control Mode Set
A control mode as shown below is selected by the MODE terminal.
MODE
0
1
Parallel
Serial
Control Method
Parallel
Serial
Function
Digital Audio interface Format Set
Control Register serial data input
Terminals
F0, F1, F2
DATA, REQ, SCK
: Digital Audio Interface Format is set directly by using F0, F1, and F2 terminals.
:
NJU8725
is controlled serial input data by 3-wire serial interface using DATA, REQ, and
SCK terminals
By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed.
Refer to
(8-5)F0,F1,F2
about function of F0, F1, and F2 terminals.
Refer to
(8)Control Register
about function of DATA, REQ, and SCK terminals.
(7-3) Mute
Mute functions by “L” signal into the MUTE terminal. In busy of mute, a current attenuation value
becomes -∞ by internal digital attenuator. And MUTE is stopped by “H” signal into the MUTE terminal, the
attenuation value returns from -∞ to previous value.
MUTE
0
1
Attenuation Level
-∞
Set Value
MUTE
MCK
Attenuation Value
Set Value
-∞
Figure 2. Mute Timing
-∞
1024/f
S
1024/f
S
Set Value
-4-
NJU8725
(8) Serial Audio Data Interface
(8-1) Input Data Format Selection
2
The digital audio interface format is selected out of I S, MSB Justified or LSB Justified, and 16 bits or 18
bits data length.
(8-2) Input Timing
Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising
edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as
shown below:
Data Format
2
IS
MSB Justified
LSB Justified
Rising Edge
Lch Input Register
Rch
Input Register
Rch
Input Register
Falling Edge
Rch Input Register
Lch
Input Register
Lch
Input Register
BCK and LRCK must be synchronized with MCK.
LRCK
BCK
DIN
Left Channel
Right Channel
15 14 13
1
0
2
15 14 13
1
0
Figure 3.1. 16 bits I S Data Format
Right Channel
LRCK
BCK
DIN
15 14 13
1 0
15 14 13
1
0
15
Left Channel
Figure 3.2. 16 bits MSB Justified Data Format
LRCK
BCK
DIN
0
Right Channel
Left Channel
15 14
3
2
1
0
15 14
3
2
1
0
Figure 3.3. 16 bits LSB Justified Data Format
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