7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
UltraLogic
t
32 Macrocell Flash CPLD
Features
Functional Description
D
D
D
D
D
32 macrocells in two logic blocks
32 I/O pins
6 dedicated inputs including 2 clock
pins
No hidden delays
High speed
f
MAX
= 143 MHz
t
PD
= 8.5 ns
t
S
= 5 ns
t
CO
= 6 ns
The CY7C371 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the F
LASH
370 family of high den
sity, high speed CPLDs. Like all members
of the F
LASH
370 family, the CY7C371 is
designed to bring the ease of use and high
performance of the 22V10 to high density
CPLDs.
The 32 macrocells in the CY7C371 are di
vided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the F
LASH
370 architec
ture are connected with an extremely fast
and predictable routing resource the
Programmable
Interconnect
Matrix
(PIM). The PIM brings flexibility, rout
ability, speed, and a uniform delay to the
interconnect.
Like all members of the F
LASH
370 family,
the CY7C371 is rich in I/O resources.
Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very sim
ple timing model. Unlike other high den
sity CPLD architectures, there are no hid
den speed delays such as fanout effects, in
terconnect delays, or expander delays. Re
gardless of the number of resources used
or the type of application, the timing pa
rameters on the CY7C371 remain the
same.
D
D
D
Electrically alterable FLASH
technology
Available in 44 pin PLCC, CLCC, and
TQFP packages
Pin compatible with the CY7C372
Logic Block Diagram
INPUTS
CLOCK
INPUTS
4
INPUT
MACROCELLS
2
INPUT/CLOCK
MACROCELLS
2
2
PIM
16 I/Os
I/O
0
-I/O
15
LOGIC
BLOCK
A
16
16
36
36
LOGIC
BLOCK
B
16 I/Os
I/O
16
-I/O
31
16
16
7c371 1
Selection Guide
7C371-143
7C371-110
7C371-83
7C371L-83
7C371-66
7C371L-66
Maximum Propagation Delay, t
PD
(ns)
Minimum Set Up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Maximum Supply
Current,
Current I
CC
(mA)
Commercial
Military/Ind.
8.5
5
6
220
10
6
6.5
175
12
10
10
175
220
12
10
10
90
110
15
12
12
175
220
15
12
12
90
110
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
D
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
December 1993 - Revised August 1995
7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
Pin Configurations
PLCC/CLCC
Top View
4
3
2
31
30
29
28
I/O
I/O
I/O
GND
CC
TQFP
Top View
31
30
29
I/O
GND
I/O
I/O
CC
I/O
I/O
I/O
28
1
0
4
3
2
1
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
6
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
I/O
27
I/O
26
I/O
25
I/O
24
CLK1/I
5
GND
I
4
I
3
I/O
23
I/O
22
I/O
21
I/O
5
I/O
6
I/O
7
I
0
I
1
GND
CLK0/I
2
I/O
8
I/O
9
I/O
10
I/O
11
1
2
3
4
5
6
7
8
9
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
I/O
27
I/O
26
I/O
25
I/O
24
CLK1/I
5
GND
I
4
I
3
I/O
23
I/O
22
I/O
21
I/O
5
I/O
6
I/O
7
I
0
I
1
GND
CLK0/I
2
I/O
8
I/O
9
I/O
10
I/O
11
7
8
9
10
11
12
13
14
15
16
17
10
11
18 19 20 21 22 23 24 25 26 27 28
7c371 2
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
CC
GND
12 13 14 15 16 17 18 19 20 21 22
7c371 3
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
GND
CC
V
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370 family. The CY7C371 includes two logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.
product term allocation is handled by software and is invisible to
the user.
I/O Macrocell
Product Term Array
The product term array in the F
LASH
370 logic block includes 36 in
puts from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72 x 86.
This large array in each logic block allows for very complex func
tions to be implemented in a single pass through the device.
Each of the macrocells on the CY7C371 has a separate associated
I/O pin. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell in
cludes a register that can be optionally bypassed. It also has polar
ity control, and two global clocks to trigger the register. The ma
crocell also features a separate feedback path to the PIM so that
the register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be as
signed to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are com
mon to more than one output can be implemented in a single prod
uct term. Product term steering and product term sharing help to
increase the effective density of the F
LASH
370 CPLDs. Note that
Maximum Ratings
The Programmable Interconnect Matrix (PIM) connects the two
logic blocks on the CY7C371 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Design Tools
Development software for the CY7C371 is available from Cy
press's
,
, and
software packages. All of these
products are based on the IEEE standard VHDL language. Cy
press also actively supports third party design tools such as
ABEL
t
, CUPL
t
, MINC, and LOG/iC
t
. Please contact your lo
cal Cypress representative for further information.
Warp2 Warp2+
V
Warp3
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . . -65
_
C to +150
_
C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55
_
C to +125
_
C
Supply Voltage to Ground Potential . . . . . . . . . -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Program Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . . 16 mA
Note:
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MIL STD 883, Method 3015)
Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Ambient
Range
Temperature
V
CC
Commercial
Military
[1]
Industrial
0
_
C to +70
_
C
-55
_
C to +125
_
C
-40
_
C to +85
_
C
V
5V ± 5%
5V ± 10%
5V ± 10%
1.
T
A
is the instant on" case temperature.
2
7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
Electrical Characteristics
Parameter
Over the Operating Range
[2]
Test Conditions
Min.
Max.
Unit
Description
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Output HIGH Voltage
V
CC
=
Min.
Min
V
CC
=
Min.
Min
I
OH
= -3.2 mA (Com'l/Ind)
I
OH
= -2.0 mA (Mil)
I
OL
= 16 mA (Com'l/Ind)
I
OL
= 12 mA (Mil)
2.4
V
V
0.5
V
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[4, 5]
Power Supply Current
Guaranteed Input Logical HIGH Voltage for all inputs
[3]
Guaranteed Input Logical LOW Voltage for all inputs
[2]
GND
2.0
-0.5
-10
-50
-30
7.0
0.8
+10
+50
-90
175
90
220
110
V
V
V
V
I
CC
m
A
m
A
mA
mA
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= 0.5V
V
CC
= Max., I
OUT
= 0 mA,
f = 1 mHz, V
IN
= GND, V
CC[6]
mHz
GND
Com'l
Com'l L
"
-66, -83
Com'l-143,
Mil/Ind
Ind L -66, -83
"
Capacitance
[4]
Description
Test Conditions
Max.
Unit
Parameter
C
IN
C
OUT
Input Capacitance
Output Capacitance
[4]
V
IN
= 5.0V at f=1 MHz
V
OUT
= 5.0V at f = 1 MHz
10
12
pF
pF
Endurance Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Notes:
Minimum Reprogramming Cycles
Normal Programming Conditions
4.
5.
100
Cycles
1.
2.
3.
See the last page of this specification for Group A subgroup testing in
formation.
These are absolute values with respect to device ground. All over
shoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. V
OUT
= 0.5V has been cho
sen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
Measured with 16 bit counter programmed into each logic block.
3
7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
AC Test Loads and Waveforms
238
319
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
W
W
(COM'L)
(MIL)
5V
238
319
W
W
(COM'L)
(MIL)
170
236
W
W
OUTPUT
(COM'L)
(MIL)
JIG AND
SCOPE
(b)
170
5 pF
236
W
W
(COM'L)
(MIL)
INCLUDING
7c371 5
7c371 4
ALL INPUT PULSES
3.0V
90%
10%
2.08V (COM'L)
2.13V (MIL)
GND
< 2 ns
< 2 ns
90%
10%
Equivalent to:
THÉVENIN EQUIVALENT
99
136
OUTPUT
W
W
(COM'L)
(MIL)
(c)
7c371 6
Parameter
V
X
Output Waveform
Measurement Level
t
ER (-)
t
ER (+)
t
EA (+)
t
EA (-)
1.5V
V
OH
0.5V
0.5V
V
X
V
X
7c371 7
2.6V
V
OL
7c371 8
1.5V
V
X
V
X
0.5V
V
OH
7c371 9
V
thc
0.5V
(d) Test Waveforms
V
OL
7c371 10
Switching Characteristics
Over the Operating Range
[7]
7C371-83
7C371-143
7C371-110
Min.
Max.
7C371L-83
Min.
Max.
7C371-66
7C371L-66
Min.
Max.
Unit
Parameter
Description
Min.
Max.
Combinatorial Mode Parameters
t
PD
t
PDL
t
PDLL
t
EA
t
ER
t
WL
t
WH
t
IS
t
IH
t
ICO
t
ICOL
Input to Combinatorial Output
Input to Output Through Transparent Input or
Output Latch
Input to Output Through Transparent Input and
Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
[4]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combina
torial Output
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch
[4]
8.5
11.5
13.5
13
13
10
13
15
14
14
12
18
20
19
19
15
22
24
24
24
ns
ns
ns
ns
ns
Input Registered/Latched Mode Parameters
2.5
2.5
2
2
12
14
3
3
2
2
14
16
4
4
3
3
19
21
5
5
4
4
24
26
ns
ns
ns
ns
ns
ns
Shaded area contains preliminary information.
Note:
6.
All AC parameters are measured with 16 outputs switching.
7.
This specification is intended to guarantee interface compatibility of
the other members of the CY7C370 family with the CY7C371. This
specification is met for the devices operating at the same ambient tem
perature and at the same power supply voltage.
4
7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
Switching Characteristics
Over the Operating Range
[6]
(continued)
Parameter
Description
Output Registered/Latched Mode Parameters
t
CO
t
S
t
H
t
CO2
t
SCS
t
SCS2
t
SL
t
HL
f
MAX1
f
MAX2
Clock or Latch Enable to Output
Set Up Time from Input to Clock or Latch
Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
Output Clock or Latch Enable to Output Clock or
Latch Enable (Through Memory Array)
Output Clock Through Array to Output Clock
(2 Pass Delay)
[4]
Set Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
Maximum Frequency with Internal Feedback
(Least of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[4]
Maximum Frequency Data Path in Output Regis
tered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
),
1/(t
S
+ t
H
), or 1/t
CO
)
[4]
Maximum Frequency with external feedback
(Lesser of 1/(t
CO
+ t
S
) and 1/(t
WL
+ t
WH
))
[4]
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x
[4, 8]
7C371-83 7C371-66
7C371-143 7C371-110 7C371L-83 7C371L-66
Min. Max. Min. Max. Min. Max. Min. Max. Unit
6
5
0
12
7
13
9
0
143
9
16.5
10
0
111
153.8
6
0
14
12
21
12
0
83.3
100
6.5
10
0
19
15
27
15
0
66.6
83.3
10
12
0
24
12
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
166.7
f
MAX3
t
OH
-t
IH
37x
91
0
80
0
50
0
41.6
0
MHz
ns
Pipelined Mode Parameters
t
ICS
f
MAX4
Input Register Clock to Output Register Clock
Maximum Frequency in Pipelined Mode (Least of
1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
), 1/(t
IS
+ t
IH
),
or 1/t
SCS
)
Asynchronous Reset Width
[4]
Asynchronous Reset Recovery Time
[4]
Asynchronous Reset to Output
Asynchronous Preset Width
[4]
7
125
9
111
12
76.9
15
62.5
ns
MHz
Reset/Preset Parameters
t
RW
t
RR
t
RO
t
PW
t
PR
t
PO
t
POR
8
10
14
8
10
14
1
10
12
16
10
12
16
1
15
17
21
15
17
21
1
20
22
26
20
22
26
1
ns
ns
ns
ns
ns
ns
Asynchronous Preset Recovery Time
[4]
Asynchronous Preset to Output
Power On Reset
[4]
m
s
Shaded area contains preliminary information.
Switching Waveforms
Combinatorial Output
INPUT
t
PD
COMBINATORIAL
OUTPUT
7c371 11
5
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