HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Document Title
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Change AC Parameter
tCRY(1.8V)
Before
50+tr(R/B#)
60+tr(R/B#)
History
Draft Date
Apr. 04. 2005
Remark
Preliminary
0.1
After
Jul. 07. 2005
Preliminary
2) Change 256Mb Package Type.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
1)
Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
CC1)
Before
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
t
RC
=50ns,
CE#=
V
IL
,
I
OUT
=0mA
t
RC
(1.8V=60ns,
3.3V=50ns)
CE#=
V
IL
,
I
OUT
=0mA
After
VIN=VOUT=0 to Vcc (max)
0.2
2)
Change AC Conditions table
3)
Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit Copy Back Program operation step
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
7) Change NOP (table 11)
Main Array
Before
After
1
2
Aug. 08. 2005
Preliminary
Spare Array
2
3
Rev 0.5 / Jun. 2006
1
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Revision History
Revision
No.
CP
Before
After
0.050
0.100
- Continued -
History
8) Correct PKG dimension (TSOP, USOP PKG)
Draft Date
Remark
9) Change VIL parameter (max.)
1.8V
Before
After
0.2xVcc
0.4
3.3V
0.2xVcc
0.8
0.2
10) Change AC Parameter
tOH
Before
After
15
10
tR (1.8V)
Before
After
12
15
tRP
30
25
tCRY (1.8V)
50+tr(R/B#)
(4)
80+tr(R/B#)
(4)
tREA
35
30
tCRY (3.3V)
50+tr(R/B#)
(4)
60+tr(R/B#)
(4)
Aug. 08. 2005
Preliminary
0.3
0.4
1) Correct USOP figure.
1) Correct Figure 32.
1) Add ECC algorithm. (1bit/512bytes)
2) Delet Preliminary.
3) Change AC Parameter
Nov. 07. 2005
Feb. 06. 2006
Preliminary
Preliminary
0.5
Before
After
tWHR
60 ns
50 ns
Jun. 20. 2006
4) Correct Read ID naming
Rev 0.5 / Jun. 2006
2
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27USXX561A
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
(with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27(U/S)S(08/16)561A-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)S(08/16)561A-T (Lead)
- HY27(U/S)S(08/16)561A-TP (Lead Free)
- HY27(U/S)S(08/16)561A-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27(U/S)S(08/16)561A-S (Lead)
- HY27(U/S)S(08/16)561A-SP (Lead Free)
- HY27(U/S)S(08/16)561A-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27(U/S)S(08/16)561A-F (Lead)
- HY27(U/S)S(08/16)561A-FP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX561A
Memory Cell Array
= (512+16) Bytes x 32 Pages x 2,048 Blocks
= (256+8) Words x 32 pages x 2,048 Blocks
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27(U/S)S08561A
- x16 device: (256 + 8 spare) Words
: HY27(U/S)S16561A
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 3.3V: 12us (max.)
1.8V: 15us (max.)
- Sequential access: 3.3V: 50ns (min.)
1.8V: 60ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
Rev 0.5 / Jun. 2006
3
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)S(08/16)561A series is a 32Mx8bit with spare 8Mx16 bit capacity. The device is offered in 1.8V
Vcc Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected
Flash cells.
A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)561A extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,
Read ID2 extension.
The Hynix HY27(U/S)S(08/16)561A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm,
FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER
HY27SS08561A
HY27SS16561A
HY27US08561A
HY27US16561A
ORIZATION
x8
x16
x8
x16
VCC RANGE
1.70 - 1.95 Volt
63FBGA / 48TSOP1 / 48USOP1
2.7V - 3.6 Volt
PACKAGE
Rev 0.5 / Jun. 2006
4
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 Only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.5 / Jun. 2006
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
