Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.
Electrical Characteristics
VCC = 2.70V to 5.5V for MIC70_P/R, VCC = 3.00V to 5.5V for MIC70_S, VCC = 3.15V to 5.5V for MIC70_T, T
A
= -40°C to 85°C
unless otherwise noted.
Parameter
Operating Voltage Range, VCC
Supply Current
Reset Voltage Threshold
MIC70_P/R
MIC70_S
MIC70_T
2.55
2.85
3.00
2.63
2.93
3.08
20
140
ISource = 200µA
ISink = 1.2mA
ISink = 50µA, VCC = 1.4V
ISource = 200µA
ISink = 1.2mA
ISource = 200µA
ISink = 500µA
0.8 x VCC
200
280
Conditions
Min
1.4
Typ
Max
5.5
30
2.70
3.00
3.15
Units
V
µA
V
Reset Threshold Hysteresis
Reset Pulse Width, t
RS
RESET Output Voltage
(MIC70_R/S/T)
mV
ms
V
0.3
0.3
V
0.3
V
0.3
RESET Output Voltage
(MIC706P)
RESET Output Voltage
(MIC708R/S/T)
Watchdog Timeout Period, t
WD
WDI Minimum Input Pulse, t
WP
WDI Threshold Voltage
WDI Input Current
WDO Output Voltage
0.8 x VCC
0.8 x VCC
1.0
1.6
2.25
sec
ns
ns
V
VIL = 0.4V, VIH = 80% of VCC
VIL = 0.4V, VIH = 80% of VCC>4.5V
VIH
VIL
WDI = 0V or VCC
ISource = 200µA
ISink = 500µA
100
50
0.7 x VCC
-1
0.8 x VCC
0.6
1
µA
V
0.3
2
MIC706P/R/S/T, MIC708R/S/T
µP
Supervisory Circuits
Electrical Characteristics
VCC = 2.70V to 5.5V for MIC70_P/R, VCC = 3.00V to 5.5V for MIC70_S, VCC = 3.15V to 5.5V for MIC70_T, T
A
= -40°C to 85°C
unless otherwise noted.
Parameter
MR Pull-Up Current
MR Pulse Width, t
MR
MR Input Threshold
MR to Reset Output Delay, t
MD
PFI Input Threshold
PFI Input Current
PFO Output Voltage
ISink = 1.2mA
ISource = 200µA
1.2
-25
0.8 x VCC
1.25
0.01
Conditions
MR = 0V
Min
20
500
150
0.6
0.7 x VCC
750
1.3
+25
0.3
nS
V
nA
V
Typ
250
Max
600
Units
µA
nS
nS
V
VCC > 4.5V
VIL
VIH
3
MIC706P/R/S/T, MIC708R/S/T
µP
Supervisory Circuits
Pin Functions
Pin No.
Pin Name
MR
MIC706
R/S/T
1
MIC706P
1
MIC708
1
Manual Reset Input forces reset outputs to assert when
pulled below 0.8V. An internal pull-up current of 250µA on
this input forces it high when left floating. This input can
also be driven from TTL or CMOS logic.
Primary supply input, +5V.
IC ground pin, 0V reference.
Power fail input. Internally connected to the power fail
comparator which is referenced to 1.25V. The power fail
output (PFO) remains high if PFI is above 1.25V. PFI
should be connected to GND or V OUT if the power fail
comparator is not used.
Power fail output. The power fail comparator is
independent of all other functions on this device.
Watchdog input. The WDI input monitors microprocessor
activity, an internal watchdog timer resets itself with each
transition on the watchdog input. If the WDI pin is held high
or low for longer than the watchdog timeout period, WDO is
forced to active low. The watchdog function cannot be
disabled.
No Connect
RESET is asserted if either V CC goes below the reset
threshold or by a low signal on the manual reset input (MR).
RESET remains asserted for one reset timeout period
(200ms) after VCC exceeds the reset threshold or after the
manual reset pin transitions from low to high. The
watchdog timer will not assert RESET unless WDO is
connected to MR.
Output for the watchdog timer. The watchdog timer resets
itself with each transition on the watchdog input. If the WDI
pin is held high or low for longer than the watchdog timeout
period, WDO is forced low. WDO will also be forced low if
VCC is below the reset threshold and will remain low until
VCC returns to a valid level.
RESET is the compliment of RESET and is asserted if
either V CC goes below the reset threshold or by a low
signal on the manual reset input (MR). RESET is suitable
for microprocessors systems that use an active high reset.
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