LNBH24L
Dual LNBS supply and control IC with step-up and I²C interface
Features
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Complete interface between LNBS and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93%@0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receivers output
voltage specification
Auxiliary modulation input (EXTM) facilitates
DiSEqC™ 1.X encoding
Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allow low power losses
Overload and over-temperature internal
protections with I²C diagnostic bits
Output voltage and output current level
diagnostic feedback by I²C bits
LNB short circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
QFN32 5 x 5 mm (ePad)
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Description
Intended for analog and digital DUAL satellite
receivers/Sat-TV, Sat-PC cards, the LNBH24L is
a monolithic voltage regulator and interface IC,
assembled in QFN 5x5 ePAD, specifically
designed to provide the 13 / 18 V power supply
and the 22 kHz tone signaling for two independent
LNB down-converters in the antenna dishes
and/or multi-switch box. In this application field, it
offers a dual tuner STBs complete solution with
extremely low component count, low power
dissipation together with simple design and I²C
standard interfacing.
Table 1.
Device summary
Order code
LNBH24LQTR
Package
QFN32 5 x 5 (Exposed pad)
Packaging
Tape and reel
March 2010
Doc ID 16857 Rev 2
1/25
www.st.com
25
Contents
LNBH24L
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
Application information (valid for each section A/B) . . . . . . . . . . . . . . . . . . 5
DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5
DISEQC™ 1.X implementation with VoTX and EXTM pin connection . . . . 5
PDC optional circuit for DISEQC™ 1.X applications using
VoTX signal on to EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 7
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1
6.2
6.3
6.4
6.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
7.2
7.3
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 15
Transmitted data (I²C bus write mode) for each sections A/B . . . . . . . . . 15
2/25
Doc ID 16857 Rev 2
LNBH24L
Contents
7.4
7.5
7.6
7.7
Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 16
Power-ON I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 17
8
9
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 16857 Rev 2
3/25
Block diagram
LNBH24L
1
Figure 1.
Block diagram
Block diagram
TTX-
A
ISEL-
A
-
ADDR-
A
-
SDA SCL
ADDR-
B
-
Vcc
Byp
Vcc -
L
ISEL-
B
-
TTX-
B
-
-
LX-
A
Controller
PWM
Rsense
PWM
Controller
Preregulator
+U.V.lockout
+P.ON reset
EN-
A
VSEL-
A
-
LX-
B
-
VSEL-
A
TTX-
A
-
I
I²C interface
P-GND-
A
-
TEN-
A
-
EN-
A
-
TEN-
B
EN-
B
-
-
VSEL-
B
TTX-
B
-
EN-
B
VSEL-
B
Rsense
P-GND-
B
-
Vup -
A
ISEL-
A
VOUT-
A
Control
-
Vup -
B
VOUT-
B
Control
-
ISEL-
B
-
VoRX-
A
TTX-
A
Linear Post-reg
-
+Protections
+Diagnostics
FB
I²C Diagnostics
²
Linear Post-reg
-
+Protections
+Diagnostics
FB
-
VoRX-
B
TTX-
B
-
VoTX-
A
EXTM-
A
-
22 kHz
Oscillator
22 kHz
Oscillator
VoTX-
B
-
EXTM-
B
-
DSQIN-
A
-
TEN-
A
TEN-
B
DSQIN-
B
-
PDC
-
A
LNBH24L
Pull Down
Controller
Pull Down
Controller
PDC
-
B
A-GND
-
4/25
Doc ID 16857 Rev 2
LNBH24L
Introduction
2
Introduction
The LNBH24L includes two completely independent sections. Unless for the V
CC
and I²C
inputs, each circuit can be separately controlled and have its independent external
components. All the below specification must be considered equal for both sections (A/B).
2.1
Application information (valid for each section A/B)
This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V,
generates the voltages (V
UP
) that let the linear post-regulator to work at a minimum
dissipated power of 0.55 W typ. @ 500 mA load per channel (the linear post-regulator drop
voltage is internally kept at V
UP
- V
OUT
= 1.1 V typ.). An under voltage lockout circuit will
disable the whole circuit when the supplied V
CC
drops below a fixed threshold (6.7 V
typically).
Note:
In this document the V
OUT
is intended as the voltage present at the linear post-regulator
output (V
oRX
pin).
2.2
DiSEqC™ data encoding
The new internal 22 kHz tone generator is factory trimmed in accordance to the standards,
and can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin
(DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the
22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) the
TTX function must be disabled setting TTX to LOW.
2.3
DiSEqC™ 1.X implementation by EXTM pin
In order to improve design flexibility and reduce the total application cost, an analogic
modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the
V
oRX
DC output voltage. An appropriate DC blocking capacitor must be used to couple the
modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter
can be removed (see
Section 5: Application circuits)
saving the external components
cost.The pin EXTM modulates the V
oRX
voltage through the series decoupling capacitor, so
that:
V
oRX( AC)
=
V
EXTM( AC)
×
G
EXTM
Where V
oRX
(AC) and V
EXTM
(AC) are, respectively, the peak to peak voltage on the V
oRX
and EXTM pins while G
EXTM
is the voltage gain from EXTM to V
oRX
.
2.4
DISEQC™ 1.X implementation with V
oTX
and EXTM pin
connection
If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz
tone generator signal available through the V
oTX
pin to drive the EXTM pin. By this way the
Doc ID 16857 Rev 2
5/25
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