PD -
97343
IRFS4010-7PPbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D
D
100V
3.3mΩ
4.0mΩ
190A
S
G
S
S
S
S
D
2
Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
c
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
e
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
190
130
740
380
2.5
± 20
26
-55 to + 175
300
10lbxin (1.1Nxm)
330
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
d
Avalanche Current
c
Repetitive Avalanche Energy
f
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θJA
Parameter
Junction-to-Case
jk
Junction-to-Ambient (PCB Mount)
ij
Typ.
–––
–––
Max.
0.40
40
Units
°C/W
www.irf.com
1
10/07/08
IRFS4010-7PPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G(int)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
Conditions
–––
0.11
3.3
–––
–––
–––
–––
–––
2.1
–––
–––
4.0
4.0
20
250
100
-100
–––
V V
GS
= 0V, I
D
= 250µA
V/°C Reference to 25°C, I
D
= 5mAc
mΩ V
GS
= 10V, I
D
= 110A
f
V V
DS
= V
GS
, I
D
= 250µA
µA V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
–––
150
36
48
102
19
56
100
48
9830
650
260
730
740
–––
230
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
V
DS
= 25V, I
D
= 110A
I
D
= 110A
V
DS
= 50V
V
GS
= 10V
f
I
D
= 110A, V
DS
=0V, V
GS
= 10V
V
DD
= 65V
I
D
= 110A
R
G
= 2.7Ω
V
GS
= 10V
f
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
h
V
GS
= 0V, V
DS
= 0V to 80V
g
210
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related)h –––
–––
Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
c
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
186
740
A
Conditions
MOSFET symbol
showing the
integral reverse
G
D
S
p-n junction diode.
––– –––
1.3
V T
J
= 25°C, I
S
= 110A, V
GS
= 0V
f
V
R
= 85V,
–––
60
–––
ns T
J
= 25°C
T
J
= 125°C
I
F
= 110A
–––
67
–––
di/dt = 100A/µs
f
––– 150 –––
nC T
J
= 25°C
T
J
= 125°C
––– 180 –––
–––
4.7
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.052mH
R
G
= 25Ω, I
AS
= 110A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
110A, di/dt
≤
1310A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
R
θJC
value shown is at time zero.
2
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IRFS4010-7PPbF
1000
TOP
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
1000
TOP
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
100
BOTTOM
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
10
100
1
4.0V
0.1
0.1
1
≤
60µs PULSE WIDTH
Tj = 25°C
4.0V
10
10
100
0.1
1
≤
60µs PULSE WIDTH
Tj = 175°C
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
Fig 2.
Typical Output Characteristics
2.5
ID = 110A
VGS = 10V
2.0
(Normalized)
ID, Drain-to-Source Current (A)
100
T J = 175°C
10
T J = 25°C
1.5
1
VDS = 50V
≤
60µs PULSE WIDTH
2
3
4
5
6
7
1.0
0.1
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS , Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
14.0
ID= 110A
VGS, Gate-to-Source Voltage (V)
12.0
10.0
8.0
6.0
4.0
2.0
0.0
VDS= 80V
VDS= 50V
C, Capacitance (pF)
10000
Ciss
1000
Coss
Crss
100
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0
25
50
75 100 125 150 175 200 225
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS4010-7PPbF
1000
10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10msec
1msec
10
T J = 25°C
1
VGS = 0V
0.1
0.0
0.5
1.0
1.5
VSD, Source-to-Drain Voltage (V)
10
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
1
10
0.1
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
200
180
160
ID, Drain Current (A)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8.
Maximum Safe Operating Area
125
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
6.0
5.0
4.0
Energy (µJ)
Fig 10.
Drain-to-Source Breakdown Voltage
1400
EAS , Single Pulse Avalanche Energy (mJ)
1200
1000
800
600
400
200
0
ID
TOP
21A
38A
BOTTOM 110A
3.0
2.0
1.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110
VDS, Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS4010-7PPbF
1
Thermal Response ( Z thJC ) °C/W
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τ
J
τ
J
τ
1
R
1
R
1
τ
2
R
2
R
2
R
3
R
3
τ
3
R
4
R
4
τ
C
τ
τ
4
Ri (°C/W)
0.02001
0.05145
0.19436
0.13433
0.000025
0.000094
0.002047
0.012818
τi
(sec)
τ
1
τ
2
τ
3
τ
4
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Ci=
τi/Ri
Ci i/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
0.0001
1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj
= 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
400
350
EAR , Avalanche Energy (mJ)
300
250
200
150
100
50
0
25
50
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 110A
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
75
100
125
150
175
Starting T J , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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