NB3N51032
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL/LVDS
Clock Generator
The NB3N51032 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 10). The NB3N51032 provides selectable
spread options of
−0.5%
and
−0.75%
for applications demanding low
Electromagnetic Interference (EMI) as well as optimum performance
with no spread option.
Features
www.onsemi.com
MARKING
DIAGRAM
16
16
NB3N
1032
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
Four Selectable Multipliers of the Input Frequency
Output Enable with Tri−State Outputs
PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant
Spread of
−0.5%, −0.75%
and No Spread
Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz
−88
dBc/Hz
1 kHz
−118
dBc/Hz
10 kHz
−131
dBc/Hz
100 kHz
−132
dBc/Hz
1 MHz
−144
dBc/Hz
10 MHz
−155
dBc/Hz
Typical Period Jitter RMS of 1.5 ps
Operating Supply Voltage Range 3.3 V
±5%
Industrial Temperature Range
−40°C
to +85°C
Functionally Compatible with IDT557−03,
IDT5V41065, IDT5V41235 with enhanced performance
These are Pb−Free Devices
V
DD
SS0 SS1
Spread Spectrum
Circuit
Clock Buffer
Crystal Oscillator
Phase
Detector
1
TSSOP−16
1
DT SUFFIX
CASE 948F
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Applications
•
•
•
•
•
•
•
•
•
•
•
Networking
Consumer
Computing and Peripherals
Industrial Equipment
PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4
Gigabit Ethernet
FB DIMM
Switch and Router
Set Top Box, LCD TV
Servers, Desktop Computers
Automated Test Equipment
End Products
X1/CLK
25 MHz Clock or
Crystal
X2
Charge
Pump
VCO
HCSL
Output
HCSL
Output
CLK0
CLK0
CLK1
CLK1
BN
V
DD
= VDDODA = VDDXD
GND = GNDODA = GNDXD
GND
S0
S1
OE
Figure 1. NB3N51032 Simplified Logic Diagram
IREF
©
Semiconductor Components Industries, LLC, 2016
September, 2017
−
Rev. 3
1
Publication Order Number:
NB3N51032/D
NB3N51032
S0
S1
SS0
X1/CLK
X2
OE
GNDXD
SS1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDXD
CLK0
CLK0
GNDODA
VDDODA
CLK1
CLK1
IREF
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
S0
S1
SS0
X1/CLK
X2
OE
GNDXD
SS1
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
I/O
Input
Input
Input
Input
Input
Input
Power Supply
Input
Output
HCSL or
LVDS Output
HCSL or
LVDS Output
Power Supply
Power Supply
HCSL or
LVDS Output
HCSL or
LVDS Output
Power Supply
Description
LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output
select table 2 for details.
LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output
select Table 2 for details.
LVTTL/LVCMOS Spread select input 0. Internal pullup resistor to VDDXD. See Spread se-
lection Table 3 for details.
Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.
Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
Output enable tri−states output when connected to GND. Internal pullup resistor to VDDXD.
Ground 0 V. This pin provides GND return path for the device.
LVTTL/LVCMOS Spread select input 1. Internal pullup resistor to VDDXD. See Spread se-
lection Table 3 for details.
Output current reference pin. Precision resistor (typ. 475
W)
is connected to set the output
current.
Inverted clock output. (For LVDS levels see Figure 10)
Noninverted clock output. (For LVDS levels see Figure 10)
Positive supply voltage pin connected to +3.3 V supply voltage.
Ground 0 V. These pins provide GND return path for the devices.
Inverted clock output. (For LVDS levels see Figure 10)
Noninverted clock output. (For LVDS levels see Figure 10)
Positive supply voltage pin connected to +3.3 V supply voltage.
www.onsemi.com
2
NB3N51032
Table 2. OUTPUT FREQUENCY SELECT TABLE
WITH 25MHz CRYSTAL
S1*
L
L
H
H
S0*
L
H
L
H
CLK Multiplier
1x
4x
5x
8x
f
CLKout
(MHz)
25
100
125
200
Recommended Crystal Parameters
*Pins S1 and S0 default high when left open.
Crystal
Frequency
Load Capacitance
Shunt Capacitance, C0
Equivalent Series Resistance
Initial Accuracy at 25
°C
Temperature Stability
Aging
Fundamental AT−Cut
25 MHz
16−20 pF
7 pF Max
50
W
Max
±20
ppm
±30
ppm
±20
ppm
Table 3. SPREAD SELECTION TABLE
SS1*
0
0
1
1
*Pins S1 and S0 default high when left open.
SS0*
0
1
0
1
Spread%
No Spread
−0.5
−0.75
No Spread
Spread Type
N/A
Down
Down
N/A
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Pull−up Resistor (Pins OE, S0, S1, SS0 and SS1)
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Value
2 kV
50 kW
Level 1
UL 94 V−0 @ 0.125 in
132000
www.onsemi.com
3
NB3N51032
Table 5. MAXIMUM RATINGS
(Note 2)
Symbol
V
DD
V
I
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply with respect to GND (VDDXD and VDDODA)
Input Voltage with respect to GND (V
IN
)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
Rating
4.6
−0.5
V to V
DD
+0.5 V
−40
to +85
−65
to +150
74
64
50
265
Unit
V
V
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS
(V
DD
= 3.3 V
±5%,
GND = 0 V, T
A
=
−40°C
to +85°C, Note 4)
Symbol
V
DD
GND
I
DD
I
DDOE
V
IH
V
IL
V
OH
V
OL
V
cross
DV
cross
Characteristic
Power Supply Voltage (VDDXD and VDDODA)
Power Supply Ground (GNDXD and GNDODA)
Power Supply Current, 200 MHz Output,
−0.75%
spread
Power Supply Current when OE is Set Low
Input HIGH Voltage (X1/CLK, S0, S1, SS0, SS1 and OE)
Input LOW Voltage (X1/CLK, S0, S1, SS0, SS1 and OE)
Output HIGH Voltage for HCSL Output (Note 5)
Output LOW Voltage for HCSL Output (Note 5)
Crossing Voltage Magnitude (Absolute) for HCSL Output (Notes 6 and 7)
Change in Magnitude of V
cross
for HCSL Output (Notes 6 and 8)
2000
GND
−
300
660
−150
250
0
550
150
Min
3.135
Typ
3.3
0
100
55
V
DD
+ 300
800
850
Max
3.465
Unit
V
V
mA
mA
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. VDDXD and VDDODA power pins must be shorted to power supply voltage V
DD
and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken with outputs terminated with R
S
= 33.2
W,
R
L
= 49.9
W,
with test load capacitance of 2
pF and current biasing resistor set at 475
W.
See Figure 9. Guaranteed by characterization.
5. Measurement taken from single−ended waveform.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
8. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the V
CROSS
for any particular system.
www.onsemi.com
4
NB3N51032
Table 7.
AC CHARACTERISTICS
(V
DD
= 3.3 V
±5%,
GND = 0 V, T
A
=
−40°C
to +85°C; Note 9)
Symbol
f
CLKIN
f
CLKOUT
F
NOISE
Clock/Crystal Input Frequency
Output Clock Frequency
Phase−Noise Performance
f
CLKOUT
= 100 Mhz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
f
CLKOUT
= 200 Mhz
f
CLKOUT
= 200 MHz
f
CLKOUT
= 200 MHz
f
CLKOUT
= 200 MHz
30
25
−88
−118
−131
−132
−144
−155
10
1.5
2.0
20
0.5
31.5
−10
40
0
7
30
10
45
175
175
50
55
700
700
125
125
3.0
33
20
3.0
5.0
35
Characteristic
Min
Typ
25
200
Max
Unit
MHz
MHz
dBc/Hz
t
JITTER
Period Jitter Peak−to−Peak (Note 10)
Period Jitter RMS (Note 10)
Cycle−Cycle RMS Jitter (Note 11)
Cycle−to−Cycle Peak to Peak Jitter (Note 11)
Phase RMS Jitter, Integration Range 12 kHz to 20 MHz
Spread Spectrum Modulation Frequency
ps
t
JIT(F)
f
MOD
SSC
RED
t
SKEW
Eppm
t
SPREAD
t
OE
t
DUTY_CYCLE
t
R
t
F
Dt
R
Dt
F
Stabilization
Time
ps
kHz
dB
ps
ppm
ms
ms
%
ps
ps
ps
ps
ms
Spectral Reduction, f
CLKOUT
of 100 MHz with
−0.5%
spread, 3
rd
Harmonic
(Note 12)
Within Device Output to Output Skew
Frequency Synthesis Error, All Outputs
Spread Spectruction Transition Time
(Stablization Time After Spread Spectrum Changes)
Output Enable/Disable Time (Note 13)
Output Clock Duty Cycle (Measured at cross point)
Output Risetime (Measured from 175 mV to 525 mV, Figure 11)
Output Falltime (Measured from 525 mV to 175 mV, Figure 11)
Output Risetime Variation (Single−Ended)
Output Falltime Variation (Single−Ended)
Stabilization Time From Powerup V
DD
= 3.3 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. VDDXD and VDDODA power pins must be shorted to power supply voltage V
DD
and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with R
S
= 33.2
W,
R
L
= 49.9
W,
with test load capacitance of 2 pF and current biasing resistor set at 475
W.
See Figure 9. Guaranteed by characterization.
10. Sampled with 10000 cycles.
11. Sampled with 1000 cycles.
12. Spread spectrum clocking enabled.
13. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH.
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
